Efficient techniques of fractional-N PLL for pervasive wireless applications

M. Azeem, U. R. Nelakuditi
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Abstract

Purpose The purpose of this paper to ensure the rapid developments in the radio frequency wireless technology, the synthesis of frequencies for pervasive wireless applications is crucial by implementing the design of low voltage and low power Fractional-N phase locked loop (PLL) for controlling medical devices to monitor remotely patients. Design/methodology/approach The developments urge a technique reliable to phase noise in designing fractional-N PLL with a new eight transistor phase frequency detector and a good linearized charge pump (CP) for speed of operation with minimum mismatches. Findings In applications for portable wireless devices, by proposing a new phase-frequency detector with the removal of dead, blind zones and a modified CP to minimize the mismatch of currents. Originality/value The results are simulated in 45 nm complementary metal oxide semiconductor generic process design kit (GPDK) technology in cadence virtuoso. The phase noise of the proposed Fractiona-N phase locked loop has–93.18, –101.4 and –117 dBc/Hz at 10 kHz, 100 kHz and 1 MHz frequency offsets, respectively, and consumes 3.3 mW from a 0.45 V supply.
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用于普及无线应用的高效分数n锁相环技术
为了保证射频无线技术的快速发展,实现低电压、低功率分数n锁相环(PLL)控制医疗设备远程监测患者的设计,频率合成是普及无线应用的关键。设计/方法/方法在设计分数n锁相环时,需要一种可靠的相位噪声检测技术,该技术采用新的八晶体管相位频率检测器和良好的线性化电荷泵(CP),以实现最小失配的操作速度。在便携式无线设备的应用中,提出了一种新的相位频率检测器,该检测器消除了死区、盲区和改进的CP,以最大限度地减少电流的不匹配。结果在cadence virtuoso中的45 nm互补金属氧化物半导体通用工艺设计套件(GPDK)技术中进行了模拟。在10 kHz、100 kHz和1 MHz频率偏置时,所提出的分数阶n锁相环的相位噪声分别为- 93.18、-101.4和-117 dBc/Hz,并在0.45 V电源下消耗3.3 mW。
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