Toward a graph-based dependence analysis framework for high level design verification

Abstract

Recent efforts to deploy FPGA's and application-specific accelerator devices in scalable data center environments has led to a resurgence in research associated with high level synthesis and design verification. The goal of this research has been to accelerate the initial design, verification and deployment process for abstract accelerator platforms. While the research associated with high level synthesis flows has provided significant gains in design acceleration, research in the verification of these designs has largely been based upon augmenting traditional methodologies. This work introduces the CoreGen high level design verification infrastructure. The goal of the CoreGen infrastructure is to provide a rapid, high level design verification infrastructure for complex, heterogeneous hardware architectures. Unlike traditional high-level verification strategies, CoreGen utilizes an intermediate representation (IR) for the target design constructed using a directed acyclic graph (DAG). CoreGen then applies classic compiler dependence analysis techniques using a multitude of graph inference and combinatorial logic solvers. The application of traditional compiler dependence analysis using directed acyclic graphs provides the ability to optimize the performance of the high level verification pipeline regardless of the target design complexity. We highlight this capability by demonstrating the verification performance scaling using a complex, heterogeneous design input. Our results indicate performance competitive with traditional optimizing compilers.