Accelerating frequent item counting with FPGA

Yuliang Sun, Zilong Wang, Sitao Huang, Lanjun Wang, Yu Wang, Rong Luo, Huazhong Yang
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引用次数: 15

Abstract

Frequent item counting is one of the most important operations in time series data mining algorithms, and the space saving algorithm is a widely used approach to solving this problem. With the rapid rising of data input speeds, the most challenging problem in frequent item counting is to meet the requirement of wire-speed processing. In this paper, we propose a streaming oriented PE-ring framework on FPGA for counting frequent items. Compared with the best existing FPGA implementation, our basic PE-ring framework saves 50% lookup table resources cost and achieves the same throughput in a more scalable way. Furthermore, we adopt SIMD-like cascaded filter for further performance improvements, which outperforms the previous work by up to 3.24 times in some data distributions.
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用FPGA加速频繁的项目计数
频繁项计数是时间序列数据挖掘算法中最重要的操作之一,而节省空间算法是解决这一问题的一种广泛使用的方法。随着数据输入速度的迅速提高,频繁计数最具挑战性的问题是如何满足线速处理的要求。本文在FPGA上提出了一种面向流的pe环框架,用于统计频繁项。与现有最佳FPGA实现相比,我们的基本pe环框架节省了50%的查找表资源成本,并以更大的可扩展性实现了相同的吞吐量。此外,为了进一步提高性能,我们采用了类似simd的级联滤波器,在一些数据分布中,性能比以前的工作高出3.24倍。
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