Hardware implementation of link aggregation in networks-on-chip

Abstract

The link aggregation (LAG) technique for networks-on-chip (NoC) is described and investigated in the paper. It is shown that LAG permits to improve considerably the NoC saturation threshold due to connection of neighboring routers with the aid of multiple physical links. The proposed work has three main contributions. The first is the description of a structure and principle of operation of a NoC with LAG. The second is the comparative analysis of the synthesis results for Stratix IV FPGA. It is shown that hardware costs of LAG and virtual channel (VC) routers are comparable. The third is the evaluation of average latency and saturation threshold in LAG NoC (8×8 mesh). The simulation of System Verilog models indicates that saturation threshold in proposed approach increases by 152% compared to VC NoC.