T. Bieniek, A. Wojtkiewicz, L. Lukasiak, R. B. Beck
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引用次数: 4
Abstract
Two different methods of ultrathin oxide formation are studied here, classical thermal oxidation and Grilox (see Borsoni et al., Microelectronics Reliability). It was proved that the quality of the passivating layer has a crucial influence on the overall properties of the gate stack in all cases, for the well established technology of Si/sub 3/N/sub 4/, as well as for HfO/sub 2/ (still under investigation). The interface trap density distributions in the Si forbidden gap for exemplary test devices are presented.
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