Clock Tree Skew Minimization with Structured Routing

Abstract

One of the goals of clock tree synthesis in ASIC design flow is skew minimization. There are several approaches used in traditional clock tree synthesis tools to achieve this goal. However, many of the approaches create a large number of clock-buffer levels while others result in congested clock routing. Increase in buffer level and routing congestion essentially triggers the problem of increase in buffer area and total power. Also the performance of the circuit is degraded due to on-chip variation in such situations. For certain fan-out number restricted designs, a few proposals with H-tree routed clock nets have been proposed to reduce the skew, but those proposals can hardly be used across various designs used in industry. Here we propose a method where skew minimization is mainly achieved by structured routing of clock nets. Finally, we show that with this proposal, for a few real designs from industry, we could reduce the skew up to 6.5% with increase in total wire delay up to 1.89% compared to when simple H-tree routing was deployed.