An innovative ultra low voltage sub-32nm SRAM voltage sense amplifier in DG-SOI technology

Abstract

Double-gate fully-depleted (DGFD) SOI circuits are regarded as the next generation ULSI circuits. In this paper we propose a high performance voltage sense amplifier in sub 32-nm fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. The proposed design improves the sensing delay and shows excellent tolerance to threshold voltage mismatch (9%) and L mismatch (9%) even at a voltage as low as 0.6 V. The proposed architecture is compared to two other architectures directly converted to DGSOI Technology and proves to be 50-60% faster and more (300-400%) insensitive to mismatch. The reliability and process variation insensitivity is also analyzed through Monte Carlo analysis.