A max mode control LDO with a good behavior at PSRR and line regulation and load regulation

Abstract

This paper proposes a max mode control low-dropout voltage regulator (LDO) with a novel structure, using MOS bias in depth linear region that control digital MOS to achieve a low ripple and a good behavior power supply rejections ratio (PSRR)at 10GHz or even higher frequency depending on load capacitance in a specified range. The LDO is designed on-chip in 40nm CMOS technology. The simulation results shows that the line regulation is 2.8mV/V and load regulation is less than 0.13mV/mA with a 100Pf as load. PSRR is improved from -40dB@10GHz, approximately. The constant output is 1.1V with minimal input voltage decreasing to 1.26V.The quiesent current is 120uA, 151.2uW under 1.26V supply.