High performance reconfigurable pipelined matrix multiplication module designer

Abstract

Matrix multiplication operations are heavily used in communication systems, video, signal and image processing applications such as echo cancellation, adaptive beamforming, and Multiple-Input Multiple-Output (MIMO) systems, and are also used in matrix factorizations such as Cholesky, LU, QR and DCT. However, it is challenging to implement a high speed matrix multiplication operator for large matrices due to the fact that the number of multiplication operations grows rapidly with functions of n3. This paper presents the implementation of a reconfigurable pipelined high speed and high precision matrix multiplication module designer for large matrices on Xilinx Virtex-5 and Spartan 3E FPGAs using high speed memory interface for data transfers.