Chia-Tsen Dai, M. Ker, Yeh-Ning Jou, Shao-Chang Huang, Geeng-Lih Lin, Jian-Hsing Lee
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引用次数: 2
Abstract
The latchup path between high-voltage (HV) PMOS and low-voltage (LV) PMOS in a 0.16-μm 30-V/1.8-V bipolar-CMOS-DMOS (BCD) technology is studied. From the experiment results on silicon chip, this path can be easily induced into latchup state during the current-trigger latchup test. Therefore, the related layout rules should be carefully specified to avoid such HV-to-LV cross-domain latchup issue.
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