Pub Date : 2018-09-01DOI: 10.23919/EOS/ESD.2018.8509690
Myeongjo Jeong, Junsik Park, Jinwoo Kim, M. Seung, Seokkiu Lee, Jingook Kim
A sense amplifier flip-flop, which is commonly used as an input receiver in a DRAM, is designed in the simplified motherboard and DIMM structures of a laptop PC. System-level ESD-induced soft failures of the sense amplifier flip-flop are measured and validated with SPICE simulation.
{"title":"Measurement and Analysis of System-level ESD-induced Soft Failures of a Sense Amplifier Flip-Flop with Pseudo Differential Inputs","authors":"Myeongjo Jeong, Junsik Park, Jinwoo Kim, M. Seung, Seokkiu Lee, Jingook Kim","doi":"10.23919/EOS/ESD.2018.8509690","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2018.8509690","url":null,"abstract":"A sense amplifier flip-flop, which is commonly used as an input receiver in a DRAM, is designed in the simplified motherboard and DIMM structures of a laptop PC. System-level ESD-induced soft failures of the sense amplifier flip-flop are measured and validated with SPICE simulation.","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121120976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EOS/ESD.2018.8509784
Y. Zhou, J. Hajjar, S. Parthasarathy, D. Clarke, Brian Moane
Compliance to system-level ESD robustness at the product level is increasingly becoming a competitive advantage. Predicting the classification test level of a design prior to fabrication is critical in achieving first pass success and also addressing key concerns in this regards. Compact models and a simulation platform have been developed to predict system-level ESD robustness.
{"title":"System Level Esd Simulation In Spice: A Holistic Approach","authors":"Y. Zhou, J. Hajjar, S. Parthasarathy, D. Clarke, Brian Moane","doi":"10.23919/EOS/ESD.2018.8509784","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2018.8509784","url":null,"abstract":"Compliance to system-level ESD robustness at the product level is increasingly becoming a competitive advantage. Predicting the classification test level of a design prior to fabrication is critical in achieving first pass success and also addressing key concerns in this regards. Compact models and a simulation platform have been developed to predict system-level ESD robustness.","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115066925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EOS/ESD.2018.8509694
D. Johnsson, K. Domanski, H. Gossner
CDM discharges exhibit a fast initial current step when the stray capacitance of the pogo pin is charged. It is demonstrated that the high slew rate can damage sensitive gate oxides. The miscorrelation of CDM and CC-TLP methodologies is addressed by applying pulses with 20 ps rise time.
{"title":"Device Failure from the Initial Current Step of a CDM Discharge","authors":"D. Johnsson, K. Domanski, H. Gossner","doi":"10.23919/EOS/ESD.2018.8509694","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2018.8509694","url":null,"abstract":"CDM discharges exhibit a fast initial current step when the stray capacitance of the pogo pin is charged. It is demonstrated that the high slew rate can damage sensitive gate oxides. The miscorrelation of CDM and CC-TLP methodologies is addressed by applying pulses with 20 ps rise time.","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117091554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EOS/ESD.2018.8509772
Chia-Tsen Dai, M. Ker, Yeh-Ning Jou, Shao-Chang Huang, Geeng-Lih Lin, Jian-Hsing Lee
The latchup path between high-voltage (HV) PMOS and low-voltage (LV) PMOS in a 0.16-μm 30-V/1.8-V bipolar-CMOS-DMOS (BCD) technology is studied. From the experiment results on silicon chip, this path can be easily induced into latchup state during the current-trigger latchup test. Therefore, the related layout rules should be carefully specified to avoid such HV-to-LV cross-domain latchup issue.
研究了0.16 μm 30 v /1.8 v双极cmos - dmos (BCD)技术中高压PMOS与低压PMOS的锁存路径。从硅片上的实验结果来看，在电流触发闭锁测试中，该路径很容易被诱导进入闭锁状态。因此，应仔细指定相关的布局规则，以避免此类高压-低压跨域锁定问题。
{"title":"Study on Latchup Path between HV-LDMOS and LV-CMOS in a 0.16-μm 30-V/1.8-V BCD Technology","authors":"Chia-Tsen Dai, M. Ker, Yeh-Ning Jou, Shao-Chang Huang, Geeng-Lih Lin, Jian-Hsing Lee","doi":"10.23919/EOS/ESD.2018.8509772","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2018.8509772","url":null,"abstract":"The latchup path between high-voltage (HV) PMOS and low-voltage (LV) PMOS in a 0.16-μm 30-V/1.8-V bipolar-CMOS-DMOS (BCD) technology is studied. From the experiment results on silicon chip, this path can be easily induced into latchup state during the current-trigger latchup test. Therefore, the related layout rules should be carefully specified to avoid such HV-to-LV cross-domain latchup issue.","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121295418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EOS/ESD.2018.8509793
Koki Narita, M. Okushima
An on-chip protection for improvements of powered ESD robustness is presented. The proposed power clamp achieved to reduce the clamping voltage against powered ESD events compared to a conventional RC-riggered clamp by extending of the big-MOS active time with also consideration to false activation.
{"title":"Low Clamping Voltage Protection for Improvements of Powered ESD Robustness","authors":"Koki Narita, M. Okushima","doi":"10.23919/EOS/ESD.2018.8509793","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2018.8509793","url":null,"abstract":"An on-chip protection for improvements of powered ESD robustness is presented. The proposed power clamp achieved to reduce the clamping voltage against powered ESD events compared to a conventional RC-riggered clamp by extending of the big-MOS active time with also consideration to false activation.","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"208 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131952655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EOS/ESD.2018.8509786
L. H. Koh, Y. H. Goh
This paper describes the grounding cables selection process in mitigating random degradation of more than 200 automated tester handlers’ parametric test yield in a back-end semiconductor factory, testing Radio Frequency Integrated Circuit ESD sensitive devices, due to stochastic high frequency ground current noise issues.
{"title":"Grounding Considerations for RFIC Automated Handling Equipment Testing","authors":"L. H. Koh, Y. H. Goh","doi":"10.23919/EOS/ESD.2018.8509786","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2018.8509786","url":null,"abstract":"This paper describes the grounding cables selection process in mitigating random degradation of more than 200 automated tester handlers’ parametric test yield in a back-end semiconductor factory, testing Radio Frequency Integrated Circuit ESD sensitive devices, due to stochastic high frequency ground current noise issues.","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133317679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EOS/ESD.2018.8509696
T. Viheriäkoski, Eira Kärjä, Pekka Horsma-aho, Reinhold Gärtner, J. Smallwood
ESD risk scenarios of conductive containers were assessed by using a system level test generator and different configurations of discharge electrodes. Energy coupling inside the container can be minimized by an applicable mechanical design. Avoidance of the direct or capacitive drain and return path mitigates energy coupling and reduces ESD risks efficiently.
{"title":"ESD Risks of Containers Made of Conductive Compounds","authors":"T. Viheriäkoski, Eira Kärjä, Pekka Horsma-aho, Reinhold Gärtner, J. Smallwood","doi":"10.23919/EOS/ESD.2018.8509696","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2018.8509696","url":null,"abstract":"ESD risk scenarios of conductive containers were assessed by using a system level test generator and different configurations of discharge electrodes. Energy coupling inside the container can be minimized by an applicable mechanical design. Avoidance of the direct or capacitive drain and return path mitigates energy coupling and reduces ESD risks efficiently.","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124380091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EOS/ESD.2018.8509774
W. Stadler, J. Niemesheim, Stefan Seidl, R. Gaertner, Toni Viheriaekoski
For objects with different sizes, distances and orientations to an electric field, potentials, charging, and discharge currents of the objects are measured in order to assess the ESD risk due to the E-field. The current rules in ANSI/ESD S20.20 and IEC 61340-5-1 might need an update to cover worst-case scenarios.
{"title":"The Risks of Electric Fields for ESD Sensitive Devices","authors":"W. Stadler, J. Niemesheim, Stefan Seidl, R. Gaertner, Toni Viheriaekoski","doi":"10.23919/EOS/ESD.2018.8509774","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2018.8509774","url":null,"abstract":"For objects with different sizes, distances and orientations to an electric field, potentials, charging, and discharge currents of the objects are measured in order to assess the ESD risk due to the E-field. The current rules in ANSI/ESD S20.20 and IEC 61340-5-1 might need an update to cover worst-case scenarios.","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123167036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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