When reconfigurable architecture meets network-on-chip

R. Soares, Ivan Saraiva Silva, A. Azevedo
{"title":"When reconfigurable architecture meets network-on-chip","authors":"R. Soares, Ivan Saraiva Silva, A. Azevedo","doi":"10.1145/1016568.1016626","DOIUrl":null,"url":null,"abstract":"This paper analyzes the utilization of a network on chip (NoC) as the communication sub-system of a reconfigurable/parallel architecture. A router was designed and implemented in SystemC to analyze the NoC. With this routers the NoCX4 was created and simulated using coarse-grained reconfigurable microprocessor as processing nodes. To perform the simulation two approaches were used. The first one uses a load generator program and communication loads between 5% and 25%. The second is the calculation of 2D-DCT coefficients.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1016568.1016626","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 15

Abstract

This paper analyzes the utilization of a network on chip (NoC) as the communication sub-system of a reconfigurable/parallel architecture. A router was designed and implemented in SystemC to analyze the NoC. With this routers the NoCX4 was created and simulated using coarse-grained reconfigurable microprocessor as processing nodes. To perform the simulation two approaches were used. The first one uses a load generator program and communication loads between 5% and 25%. The second is the calculation of 2D-DCT coefficients.
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当可重构架构遇到片上网络时
本文分析了片上网络(NoC)作为可重构/并行体系结构的通信子系统的应用。在SystemC中设计并实现了一个路由器来分析NoC。使用这些路由器创建了NoCX4,并使用粗粒度可重构微处理器作为处理节点进行了模拟。为了进行仿真,采用了两种方法。第一种使用负载发生器程序,通信负载在5%到25%之间。二是2D-DCT系数的计算。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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