Leakage power consumption is a growing concern in integrated circuit design. Nanometer CMOS transistors are characterized by significant sub-threshold and gate leakage currents and feature size scaling is exacerbating this problem. In today's technologies (i.e., 90 nm), sub-threshold leakage currents are still dominant with respect to gate currents (although the trend shows that the latter grows more rapidly as technology scales). In this talk, we introduce a complete methodology for sub-threshold leakage current reduction based on the concept of sleep transistor insertion. Our insertion approach is layout-aware and it is fully compatible with industry-standard row-based layout styles and the supporting design tools. Sleep transistor cells are chosen from a library of cells that has been designed for high layout efficiency. These cells are inserted at the boundaries of existing cell rows, causing minimal disruption in placement and routing. The methodology ensures tight control of area and delay overheads, as it allows to selectively choose which gates in the netlist are connected to the sleep transistors. The effectiveness of the sleep transistor insertion methodology has been benchmarked on a set of design examples for which a physical implementation was obtained through commercial EDA tools; the results we have achieved show a reduction of leakage power ranging from 74% to 83%, depending on the circuit.
{"title":"Leakage power optimization in standard-cell designs","authors":"E. Macii","doi":"10.1145/1016568.1016571","DOIUrl":"https://doi.org/10.1145/1016568.1016571","url":null,"abstract":"Leakage power consumption is a growing concern in integrated circuit design. Nanometer CMOS transistors are characterized by significant sub-threshold and gate leakage currents and feature size scaling is exacerbating this problem. In today's technologies (i.e., 90 nm), sub-threshold leakage currents are still dominant with respect to gate currents (although the trend shows that the latter grows more rapidly as technology scales). In this talk, we introduce a complete methodology for sub-threshold leakage current reduction based on the concept of sleep transistor insertion. Our insertion approach is layout-aware and it is fully compatible with industry-standard row-based layout styles and the supporting design tools. Sleep transistor cells are chosen from a library of cells that has been designed for high layout efficiency. These cells are inserted at the boundaries of existing cell rows, causing minimal disruption in placement and routing. The methodology ensures tight control of area and delay overheads, as it allows to selectively choose which gates in the netlist are connected to the sleep transistors. The effectiveness of the sleep transistor insertion methodology has been benchmarked on a set of design examples for which a physical implementation was obtained through commercial EDA tools; the results we have achieved show a reduction of leakage power ranging from 74% to 83%, depending on the circuit.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114624566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present a pseudo random bit sequence (PRBS) generator with a sequence length of 2/sup 7/-1. The circuit uses a 7 bit full rate shift register with a linear XOR feedback and works up to data rates of 13 Gb/s. The PRBS generator features a divide by 2 trigger divider, two 3 bit shifted outputs and an autostart logic. The circuit draws 137 mA from a single 1.5 V supply. The circuit is manufactured in 120 nm bulk CMOS technology.
{"title":"A low power 13-Gb/s 2/sup 7/-1 pseudo random bit sequence generator IC in 120 nm bulk CMOS","authors":"H. Wohlmuth, D. Kehrer","doi":"10.1145/1016568.1016630","DOIUrl":"https://doi.org/10.1145/1016568.1016630","url":null,"abstract":"We present a pseudo random bit sequence (PRBS) generator with a sequence length of 2/sup 7/-1. The circuit uses a 7 bit full rate shift register with a linear XOR feedback and works up to data rates of 13 Gb/s. The PRBS generator features a divide by 2 trigger divider, two 3 bit shifted outputs and an autostart logic. The circuit draws 137 mA from a single 1.5 V supply. The circuit is manufactured in 120 nm bulk CMOS technology.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"11 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124184635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Jacomet, J. Goette, Venanz Zbinden, Christian Narvaez
Conventional sigma-delta (/spl Sigma//spl Delta/) analog-to-digital (A/D) converters are based on an analog /spl Sigma//spl Delta/ modulator followed by a digital filter. In this paper we propose a new architecture of a first-order /spl Sigma//spl Delta/ modulator that needs no active analog components. We call this /spl Sigma//spl Delta/ modulator "digital-only," and implement with it A/D converters in FPGA's or directly in the software of microprocessors. We here discuss aspects of the dynamic behavior of the proposed structure.
{"title":"On the dynamic behavior of a novel digital-only sigma-delta A/D converter","authors":"M. Jacomet, J. Goette, Venanz Zbinden, Christian Narvaez","doi":"10.1145/1016568.1016628","DOIUrl":"https://doi.org/10.1145/1016568.1016628","url":null,"abstract":"Conventional sigma-delta (/spl Sigma//spl Delta/) analog-to-digital (A/D) converters are based on an analog /spl Sigma//spl Delta/ modulator followed by a digital filter. In this paper we propose a new architecture of a first-order /spl Sigma//spl Delta/ modulator that needs no active analog components. We call this /spl Sigma//spl Delta/ modulator \"digital-only,\" and implement with it A/D converters in FPGA's or directly in the software of microprocessors. We here discuss aspects of the dynamic behavior of the proposed structure.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130169403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A design sequence for a LC-tank voltage controlled oscillator - VCO - in CMOS for radio frequency is presented in this paper. Details about the design of the components are shown. Among these details, it is a method to reach the active components (transistors) based on simulations using models given by the foundry. A VCO with a frequency range from 2.4 GHz to 2.5 GHz has been designed to validate the method. Due to access facilities it had been chosen the AMS 0.35 /spl mu/m CMOS as fabrication technology. The VCO had been fabricated and the measurements done are compatible with the simulations. The good agreement between the measurements and the simulations show that the design sequence is correct.
{"title":"Design sequence for a LC-tank voltage controlled oscillator in CMOS for RF","authors":"J. Neto","doi":"10.1145/1016568.1016595","DOIUrl":"https://doi.org/10.1145/1016568.1016595","url":null,"abstract":"A design sequence for a LC-tank voltage controlled oscillator - VCO - in CMOS for radio frequency is presented in this paper. Details about the design of the components are shown. Among these details, it is a method to reach the active components (transistors) based on simulations using models given by the foundry. A VCO with a frequency range from 2.4 GHz to 2.5 GHz has been designed to validate the method. Due to access facilities it had been chosen the AMS 0.35 /spl mu/m CMOS as fabrication technology. The VCO had been fabricated and the measurements done are compatible with the simulations. The good agreement between the measurements and the simulations show that the design sequence is correct.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131223950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. S. Dhillon, A. U. Diril, A. Chatterjee, A. Singh
Domino logic is a commonly used alternative to CMOS logic for designing circuits with high speed and/or low area requirements. Although it provides higher speed and lower area, domino logic has relatively higher dynamic power consumption than CMOS logic due to a precharge/evaluate based operation. We propose a novel low-power domino gate design and also a methodology to use these low-power but slower gates with regular domino logic gates in combinational circuits to achieve low-power operation without changing the circuit delay. We apply our method on ISCAS'85 benchmark circuits and find that replacing the off-critical path normal domino gates with the proposed low-power gates reduces power consumption of the circuits by 20.6% on the average without affecting the circuit timing.
{"title":"Low-power dual V/sub th/ pseudo dual V/sub dd/ domino circuits","authors":"Y. S. Dhillon, A. U. Diril, A. Chatterjee, A. Singh","doi":"10.1145/1016568.1016640","DOIUrl":"https://doi.org/10.1145/1016568.1016640","url":null,"abstract":"Domino logic is a commonly used alternative to CMOS logic for designing circuits with high speed and/or low area requirements. Although it provides higher speed and lower area, domino logic has relatively higher dynamic power consumption than CMOS logic due to a precharge/evaluate based operation. We propose a novel low-power domino gate design and also a methodology to use these low-power but slower gates with regular domino logic gates in combinational circuits to achieve low-power operation without changing the circuit delay. We apply our method on ISCAS'85 benchmark circuits and find that replacing the off-critical path normal domino gates with the proposed low-power gates reduces power consumption of the circuits by 20.6% on the average without affecting the circuit timing.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133414325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Long past are the days when programmable logic (FPGAs and CPLDs) were used only for prototyping and interface logic. Today's modem devices have complicated architectures with close to 200,000 logic elements and flip-flops, dedicated blocks for DSP processing, embedded memories and processors, and support many I/O standards including high-speed serial and now embedded tranceivers. The CAD software to support FPGAs has grown in sophistication and scope to support these larger, more complicated, devices and the size of software groups at FPGA vendors is now larger than all but the biggest EDA companies. Most user designs are now complete systems and go to production as an FPGA. In this tutorial we talk about recent FPGA and CPLD device architectures and CAD tools, with an emphasis on the interaction between the software and the architecture, and how this has driven recent evolutions and revolutions in PLD architecture. We also discuss the software behind the FPGA - the synthesis, place and route algorithms and CAD flow used to convert a high-level design into a bitstream to program the device. Finally, we discuss issues in designing hardware for FPGAs, including coding styles to achieve better performance and area, and effective use of dedicated resources on FPGAs.
{"title":"Architecture and CAD for FPGAs","authors":"M. Hutton","doi":"10.1145/1016568.1016577","DOIUrl":"https://doi.org/10.1145/1016568.1016577","url":null,"abstract":"Long past are the days when programmable logic (FPGAs and CPLDs) were used only for prototyping and interface logic. Today's modem devices have complicated architectures with close to 200,000 logic elements and flip-flops, dedicated blocks for DSP processing, embedded memories and processors, and support many I/O standards including high-speed serial and now embedded tranceivers. The CAD software to support FPGAs has grown in sophistication and scope to support these larger, more complicated, devices and the size of software groups at FPGA vendors is now larger than all but the biggest EDA companies. Most user designs are now complete systems and go to production as an FPGA. In this tutorial we talk about recent FPGA and CPLD device architectures and CAD tools, with an emphasis on the interaction between the software and the architecture, and how this has driven recent evolutions and revolutions in PLD architecture. We also discuss the software behind the FPGA - the synthesis, place and route algorithms and CAD flow used to convert a high-level design into a bitstream to program the device. Finally, we discuss issues in designing hardware for FPGAs, including coding styles to achieve better performance and area, and effective use of dedicated resources on FPGAs.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"47 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123188049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Murgan, C. Schlachta, M. Petrov, L. Indrusiak, A. Ortiz, M. Glesner, R. Reis
With continuously increasing on-chip frequencies and shortening signal rise time, inductance effects pose severe difficulties on efficient timing analysis. This work analyses the effects on different timing parameters of the inductive coupling in long and intermediate high-frequency on-chip interconnects. We show that crosstalk, noise, signal integrity, signal rise and fall times, all depend on the data toggling pattern. Moreover, the conclusion is drawn that the worst and best case switching patterns are not necessarily similar for capacitively coupled dominant and for mainly inductively coupled lines.
{"title":"Accurate capture of timing parameters in inductively-coupled on-chip interconnects","authors":"T. Murgan, C. Schlachta, M. Petrov, L. Indrusiak, A. Ortiz, M. Glesner, R. Reis","doi":"10.1145/1016568.1016604","DOIUrl":"https://doi.org/10.1145/1016568.1016604","url":null,"abstract":"With continuously increasing on-chip frequencies and shortening signal rise time, inductance effects pose severe difficulties on efficient timing analysis. This work analyses the effects on different timing parameters of the inductive coupling in long and intermediate high-frequency on-chip interconnects. We show that crosstalk, noise, signal integrity, signal rise and fall times, all depend on the data toggling pattern. Moreover, the conclusion is drawn that the worst and best case switching patterns are not necessarily similar for capacitively coupled dominant and for mainly inductively coupled lines.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128072581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Safety-critical applications are now common where both digital and mechanical components are deployed, as in the automotive fields. The analysis of the dependability of such systems is a particularly complex task that mandates modeling capabilities in both the discrete and in the continuous domains. To tackle this problem a multi-level approach is presented here, which is based on abstract functional models to capture the behavior of the whole system, and on detailed structural models to cope with the details of system components. In this paper, we describe how the interaction between the two levels of abstraction is managed to provide accurate analysis of the dependability of the whole system. In particular, the proposed technique is shown to be able to identify faults affecting the CAN network whose effects are most likely to be critical for vehicle's dynamic. Exploiting the information about the effects of these faults, they can then be further analyzed at the higher level of details.
{"title":"A multi-level approach to the dependability analysis of networked systems based on the CAN protocol","authors":"Fulvio Corno, J. P. Acle, M. Reorda, M. Violante","doi":"10.1145/1016568.1016593","DOIUrl":"https://doi.org/10.1145/1016568.1016593","url":null,"abstract":"Safety-critical applications are now common where both digital and mechanical components are deployed, as in the automotive fields. The analysis of the dependability of such systems is a particularly complex task that mandates modeling capabilities in both the discrete and in the continuous domains. To tackle this problem a multi-level approach is presented here, which is based on abstract functional models to capture the behavior of the whole system, and on detailed structural models to cope with the details of system components. In this paper, we describe how the interaction between the two levels of abstraction is managed to provide accurate analysis of the dependability of the whole system. In particular, the proposed technique is shown to be able to identify faults affecting the CAN network whose effects are most likely to be critical for vehicle's dynamic. Exploiting the information about the effects of these faults, they can then be further analyzed at the higher level of details.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116968671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Networks-on-Chip (NoCs) emerge as the solution for the problem of interconnecting cores (or IPs) in systems-on-chip (SoCs) which require reusable and scalable communication architectures. The building block of a NoC is its router (or switch), whose architecture has great impact on the costs and on the performance of the network. This work presents a parameterizable router architecture for NoCs which is based on a canonical template and on a library of building components offering different alternatives and implementations for the circuits used for packet forwarding in a NoC. Such features allow to explore the NoC design space in order to obtain a router configuration which best fits the performance requirements of a target application at lower silicon costs. We describe the router architecture and present some synthesis results which demonstrate the feasibility of this new router.
{"title":"ParIS: a parameterizable interconnect switch for networks-on-chip","authors":"C. Zeferino, Frederico G. M. E. Santo, A. Susin","doi":"10.1145/1016568.1016624","DOIUrl":"https://doi.org/10.1145/1016568.1016624","url":null,"abstract":"Networks-on-Chip (NoCs) emerge as the solution for the problem of interconnecting cores (or IPs) in systems-on-chip (SoCs) which require reusable and scalable communication architectures. The building block of a NoC is its router (or switch), whose architecture has great impact on the costs and on the performance of the network. This work presents a parameterizable router architecture for NoCs which is based on a canonical template and on a library of building components offering different alternatives and implementations for the circuits used for packet forwarding in a NoC. Such features allow to explore the NoC design space in order to obtain a router configuration which best fits the performance requirements of a target application at lower silicon costs. We describe the router architecture and present some synthesis results which demonstrate the feasibility of this new router.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125060096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. P. Moreira, E. Kerhervé, P. Jarry, A. Shirakawa, D. Belot
This paper presents a dual-mode RF receiver front-end consisting of a LNA, an active single-ended-to-differential converter and a downconversion mixer. It uses a high performance 0.25-/spl mu/m 60-GHz f/sub T/ SiGe:C BiCMOS7RF integration technology from STMicroelectronics. The proposed RF receiver front-end (RFFE) is targeted to GSM1800 (1805-1880MHz) and WCDMA-FDD (2110-2170MHz) systems. The main motivation of this work is to share as many elements as possible in both modes avoiding conventional parallel receiver chains, which is not a cost-efficient solution. The overall RFFE achievable gain is around 40dB in both modes. The overall front-end noise figure (Friis formula) is less than 1.3dB for GSM1800 and 1.6dB for WCDMA mode. These performances fulfil the systems requirements. The complete RFFE circuit consumes 18 mW in both operation modes at 2.5 V supply voltage.
{"title":"Dual-mode RF receiver front-end using a 0.25-/spl mu/m 60-GHz f/sub T/ SiGe:C BiCMOS7RF technology","authors":"C. P. Moreira, E. Kerhervé, P. Jarry, A. Shirakawa, D. Belot","doi":"10.1145/1016568.1016597","DOIUrl":"https://doi.org/10.1145/1016568.1016597","url":null,"abstract":"This paper presents a dual-mode RF receiver front-end consisting of a LNA, an active single-ended-to-differential converter and a downconversion mixer. It uses a high performance 0.25-/spl mu/m 60-GHz f/sub T/ SiGe:C BiCMOS7RF integration technology from STMicroelectronics. The proposed RF receiver front-end (RFFE) is targeted to GSM1800 (1805-1880MHz) and WCDMA-FDD (2110-2170MHz) systems. The main motivation of this work is to share as many elements as possible in both modes avoiding conventional parallel receiver chains, which is not a cost-efficient solution. The overall RFFE achievable gain is around 40dB in both modes. The overall front-end noise figure (Friis formula) is less than 1.3dB for GSM1800 and 1.6dB for WCDMA mode. These performances fulfil the systems requirements. The complete RFFE circuit consumes 18 mW in both operation modes at 2.5 V supply voltage.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122818346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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