{"title":"PHDPLL for SONET desynchronizer","authors":"Chii-Min Loau, Ji-Tsu Wu","doi":"10.1109/GLOCOM.1991.188418","DOIUrl":null,"url":null,"abstract":"A novel DPLL (digital phase-locked loop) has been designed and implemented. A novel phase locking technique called phase-hopping was developed. Key features of the phase-hopping DPLL (PHDPLL) are high-speed desynchronization and very narrow bandwidth (below 1 Hz). Moreover, it can be integrated with other operation circuits on a single chip by VLSI technology. Loop characteristics of the PHDPLL have been analyzed and verified by software simulation and hardware test. The optimal parameters and performance of the PHDPLL for SONET (Synchronous Optical NETwork) desynchronizer applications are presented. When the loop bandwidth of the PHDPLL is below 0.66 Hz, it is observed that the desynchronizer's output jitter meets the 1.5 unit interval peak-to-peak jitter specification.<<ETX>>","PeriodicalId":343080,"journal":{"name":"IEEE Global Telecommunications Conference GLOBECOM '91: Countdown to the New Millennium. Conference Record","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Global Telecommunications Conference GLOBECOM '91: Countdown to the New Millennium. Conference Record","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GLOCOM.1991.188418","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A novel DPLL (digital phase-locked loop) has been designed and implemented. A novel phase locking technique called phase-hopping was developed. Key features of the phase-hopping DPLL (PHDPLL) are high-speed desynchronization and very narrow bandwidth (below 1 Hz). Moreover, it can be integrated with other operation circuits on a single chip by VLSI technology. Loop characteristics of the PHDPLL have been analyzed and verified by software simulation and hardware test. The optimal parameters and performance of the PHDPLL for SONET (Synchronous Optical NETwork) desynchronizer applications are presented. When the loop bandwidth of the PHDPLL is below 0.66 Hz, it is observed that the desynchronizer's output jitter meets the 1.5 unit interval peak-to-peak jitter specification.<>
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