J. Nahas, T. Andre, Chitra K. Subramanian, B. Garni, H. Lin, A. Omair, W. Martino
{"title":"A 4Mb 0.18 /spl mu/m 1T1MTJ Toggle MRAM memory","authors":"J. Nahas, T. Andre, Chitra K. Subramanian, B. Garni, H. Lin, A. Omair, W. Martino","doi":"10.1109/ISSCC.2004.1332585","DOIUrl":null,"url":null,"abstract":"The 4.5/spl times/6.3mm/sup 2/ 25ns cycle-time 4Mb Toggle MRAM memory, built in 0.18 /spl mu/m 5M CMOS technology, uses a 1.55 /spl mu/m/sup 2/ bit cell with a single toggling magneto tunnel junction. The memory uses uni-directional programming currents with isolated write and read paths and balanced current mirror sense amplifier.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2004.1332585","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
Abstract
The 4.5/spl times/6.3mm/sup 2/ 25ns cycle-time 4Mb Toggle MRAM memory, built in 0.18 /spl mu/m 5M CMOS technology, uses a 1.55 /spl mu/m/sup 2/ bit cell with a single toggling magneto tunnel junction. The memory uses uni-directional programming currents with isolated write and read paths and balanced current mirror sense amplifier.
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