{"title":"A feasibility study of novel packaging technology for low cost and high performance systems","authors":"D. Iguchi, H. Umekawa","doi":"10.1109/ICSJ.2014.7009624","DOIUrl":null,"url":null,"abstract":"We have introduced a packaging technology utilizing high-dielectric ultra thin film between power and ground planes not as an embedded capacitor but a low impedance power distribution route directly connected to the chip. In this study the Power Distribution Network (PDN) characteristics of this structure were analyzed in detail using 3-d electromagnetic modeling in order to evaluate the feasibility of this technology. The calculated PDN impedance of the interposer used in the previous study shows good agreement with the measured impedance. Then we introduce a generic modeling technique of PDN for large scale System on Chips (SoCs) and extensive parametric study was done to determine the optimized structure and parameters for power distribution of actual SoCs.","PeriodicalId":362502,"journal":{"name":"IEEE CPMT Symposium Japan 2014","volume":"262 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE CPMT Symposium Japan 2014","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSJ.2014.7009624","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
We have introduced a packaging technology utilizing high-dielectric ultra thin film between power and ground planes not as an embedded capacitor but a low impedance power distribution route directly connected to the chip. In this study the Power Distribution Network (PDN) characteristics of this structure were analyzed in detail using 3-d electromagnetic modeling in order to evaluate the feasibility of this technology. The calculated PDN impedance of the interposer used in the previous study shows good agreement with the measured impedance. Then we introduce a generic modeling technique of PDN for large scale System on Chips (SoCs) and extensive parametric study was done to determine the optimized structure and parameters for power distribution of actual SoCs.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
