{"title":"Power efficient instruction cache for wide-issue processors","authors":"A.-M. Badulescu, A. Veidenbaum","doi":"10.1109/IWIA.2001.955192","DOIUrl":null,"url":null,"abstract":"The paper focuses on reducing power in instruction cache by eliminating the fetching of instructions that are not needed from a cache line. We propose a mechanism that predicts which instructions are going to be used out of a cache line before that line is fetched into the instruction buffer. The average instruction cache power savings obtained by using our fetch predictor is 22% for SPEC95 benchmark suite.","PeriodicalId":388942,"journal":{"name":"2001 Innovative Architecture for Future Generation High-Performance Processors and Systems","volume":"160 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2001 Innovative Architecture for Future Generation High-Performance Processors and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWIA.2001.955192","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
The paper focuses on reducing power in instruction cache by eliminating the fetching of instructions that are not needed from a cache line. We propose a mechanism that predicts which instructions are going to be used out of a cache line before that line is fetched into the instruction buffer. The average instruction cache power savings obtained by using our fetch predictor is 22% for SPEC95 benchmark suite.
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