H. San, Y. Jingu, H. Wada, H. Hagiwara, A. Hayakawa, J. Kudoh, K. Yahagi, T. Matsuura, H. Nakane, H. Kobayashi, M. Hotta, T. Tsukada, K. Mashiko, A. Wada
{"title":"A Multibit Complex Bandpass AZAD Modulator with I, Q Dynamic Matching and DWA Algorithm","authors":"H. San, Y. Jingu, H. Wada, H. Hagiwara, A. Hayakawa, J. Kudoh, K. Yahagi, T. Matsuura, H. Nakane, H. Kobayashi, M. Hotta, T. Tsukada, K. Mashiko, A. Wada","doi":"10.1109/ASSCC.2006.357850","DOIUrl":null,"url":null,"abstract":"A second-order multi-bit switched-capacitor complex bandpass DeltaSigmaAD modulator has been designed and fabricated for application to low-IF receivers in wireless communication systems such as Bluetooth and WLAN. We propose a new structure of a complex bandpass filter in forward path with I, Q dynamic matching which is equivalent to the conventional one but it can be divided into two separate parts. As a result, the DeltaSigma modulator which constituted with our proposed complex filter can be completely divided into two separate parts too, and there are not any signal line crossing between the upper and lower paths by a complex filter and feedback from DACs. Therefore, the layout design of the modulator can be greatly simplified. Nine-level two quantizers and four DACs are used in the modulator for lower power implementation and higher SNDR, but the nonlinearities of DACs are not noise-shaped and the SNDR of the DeltaSigma ADC degrades. We have employed a new complex bandpass data-weighted averaging (DWA) algorithm to suppress nonlinearity effects of multibit DACs in complex form to achieve high accuracy; it can be realized just by adding simple digital circuitry. Implemented in a 0.18-mum CMOS process and at 2.8 V supply, the modulator achieves a measured peak signal-to-noise-and-distortion (SNDR) of 64.5 dB at 20 MS/s with a signal bandwidth of 78 kHz while dissipating 28.4 mW and occupying a chip area of 1.82 mm2.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"61 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2006.357850","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
A second-order multi-bit switched-capacitor complex bandpass DeltaSigmaAD modulator has been designed and fabricated for application to low-IF receivers in wireless communication systems such as Bluetooth and WLAN. We propose a new structure of a complex bandpass filter in forward path with I, Q dynamic matching which is equivalent to the conventional one but it can be divided into two separate parts. As a result, the DeltaSigma modulator which constituted with our proposed complex filter can be completely divided into two separate parts too, and there are not any signal line crossing between the upper and lower paths by a complex filter and feedback from DACs. Therefore, the layout design of the modulator can be greatly simplified. Nine-level two quantizers and four DACs are used in the modulator for lower power implementation and higher SNDR, but the nonlinearities of DACs are not noise-shaped and the SNDR of the DeltaSigma ADC degrades. We have employed a new complex bandpass data-weighted averaging (DWA) algorithm to suppress nonlinearity effects of multibit DACs in complex form to achieve high accuracy; it can be realized just by adding simple digital circuitry. Implemented in a 0.18-mum CMOS process and at 2.8 V supply, the modulator achieves a measured peak signal-to-noise-and-distortion (SNDR) of 64.5 dB at 20 MS/s with a signal bandwidth of 78 kHz while dissipating 28.4 mW and occupying a chip area of 1.82 mm2.