A Multibit Complex Bandpass AZAD Modulator with I, Q Dynamic Matching and DWA Algorithm

H. San, Y. Jingu, H. Wada, H. Hagiwara, A. Hayakawa, J. Kudoh, K. Yahagi, T. Matsuura, H. Nakane, H. Kobayashi, M. Hotta, T. Tsukada, K. Mashiko, A. Wada
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引用次数: 9

Abstract

A second-order multi-bit switched-capacitor complex bandpass DeltaSigmaAD modulator has been designed and fabricated for application to low-IF receivers in wireless communication systems such as Bluetooth and WLAN. We propose a new structure of a complex bandpass filter in forward path with I, Q dynamic matching which is equivalent to the conventional one but it can be divided into two separate parts. As a result, the DeltaSigma modulator which constituted with our proposed complex filter can be completely divided into two separate parts too, and there are not any signal line crossing between the upper and lower paths by a complex filter and feedback from DACs. Therefore, the layout design of the modulator can be greatly simplified. Nine-level two quantizers and four DACs are used in the modulator for lower power implementation and higher SNDR, but the nonlinearities of DACs are not noise-shaped and the SNDR of the DeltaSigma ADC degrades. We have employed a new complex bandpass data-weighted averaging (DWA) algorithm to suppress nonlinearity effects of multibit DACs in complex form to achieve high accuracy; it can be realized just by adding simple digital circuitry. Implemented in a 0.18-mum CMOS process and at 2.8 V supply, the modulator achieves a measured peak signal-to-noise-and-distortion (SNDR) of 64.5 dB at 20 MS/s with a signal bandwidth of 78 kHz while dissipating 28.4 mW and occupying a chip area of 1.82 mm2.
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一种具有I、Q动态匹配和DWA算法的多位复带通AZAD调制器
设计并制作了一种二阶多比特开关电容复合带通DeltaSigmaAD调制器,用于蓝牙和WLAN等无线通信系统中的低中频接收机。提出了一种具有I, Q动态匹配的前向复杂带通滤波器的新结构,它与传统的带通滤波器等效,但可以分为两个独立的部分。因此,由我们提出的复杂滤波器构成的DeltaSigma调制器也可以完全分为两个独立的部分,并且没有任何信号线通过复杂滤波器和dac的反馈在上下路径之间交叉。因此,可以大大简化调制器的布局设计。调制器中采用了9级二量化器和4个dac,以实现低功耗和高SNDR,但dac的非线性不是噪声形的,DeltaSigma ADC的SNDR会下降。我们采用了一种新的复杂带通数据加权平均(DWA)算法来抑制复杂形式的多位dac的非线性效应,以达到较高的精度;只需添加简单的数字电路即可实现。该调制器采用0.18 μ m CMOS工艺,在2.8 V电源下,在20 MS/s下实现了64.5 dB的峰值信噪比和失真(SNDR),信号带宽为78 kHz,功耗为28.4 mW,芯片面积为1.82 mm2。
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