{"title":"Run-time Prediction of the Optimal Performance Point in DVS-based Dynamic Thermal Management","authors":"Junyoung Park, H. M. Ustun, J. Abraham","doi":"10.1109/VLSID.2012.63","DOIUrl":null,"url":null,"abstract":"Due to the increasing trend toward greater processor power density and computationally intensive applications, Dynamic Thermal Management (DTM) has become an essential technique in modern processors. Among many DTM techniques, Dynamic Voltage Scaling (DVS) is widely used because of its chief virtue - a cubic reduction in power at the relatively minor cost of a linear performance penalty. Because this reduction comes at a cost in execution speed, a key point of DVS-based DTM research is how accurately the processor predicts the optimal performance point where it can meet the thermal constraints while also minimizing the performance penalty. In this paper, we propose a new DVS-based DTM technique that makes the prediction of the optimal performance point more accurate. To achieve this, run-time prediction techniques are used and different power compositions due to process variations are considered from a VLSI perspective. The prediction process is performed by referring to one of the Look-Up Tables (LUTs) prepared during design time and also the average clock enable ratio that is dynamically calculated at run time. The simulation results show that we can achieve maximum processor performance while keeping the processor temperature from exceeding the threshold temperature.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"55 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 25th International Conference on VLSI Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSID.2012.63","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
Due to the increasing trend toward greater processor power density and computationally intensive applications, Dynamic Thermal Management (DTM) has become an essential technique in modern processors. Among many DTM techniques, Dynamic Voltage Scaling (DVS) is widely used because of its chief virtue - a cubic reduction in power at the relatively minor cost of a linear performance penalty. Because this reduction comes at a cost in execution speed, a key point of DVS-based DTM research is how accurately the processor predicts the optimal performance point where it can meet the thermal constraints while also minimizing the performance penalty. In this paper, we propose a new DVS-based DTM technique that makes the prediction of the optimal performance point more accurate. To achieve this, run-time prediction techniques are used and different power compositions due to process variations are considered from a VLSI perspective. The prediction process is performed by referring to one of the Look-Up Tables (LUTs) prepared during design time and also the average clock enable ratio that is dynamically calculated at run time. The simulation results show that we can achieve maximum processor performance while keeping the processor temperature from exceeding the threshold temperature.