VSPEC constraints modeling and evaluation

A. Rajkhowa, P. Alexander
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引用次数: 1

Abstract

Performance constraints play a key role in VLSI design. Performance constraints evaluation help in discovering requirements specification errors at an early stage in the design process when they are easy to fix. VSPEC is a requirements specification language for digital systems that contains a standard method for describing constraints. The paper presents a method of evaluating and verifying these constraints. Performance Description Language (PDL) is used for evaluation. The system is implemented within the ORBIT design environment.
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VSPEC约束建模和评估
性能约束在超大规模集成电路设计中起着关键作用。性能约束评估有助于在设计过程的早期阶段发现需求规范错误,因为这些错误很容易修复。VSPEC是数字系统的需求规范语言,它包含描述约束的标准方法。本文提出了一种评估和验证这些约束的方法。性能描述语言(PDL)用于评估。该系统在ORBIT设计环境中实现。
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