A methodology to evaluate the aging impact on flip-flops performance

Abstract

The impact of aging effects, in terms of circuit performance and reliability, is one of the new recent challenges in VLSI design targeting the most advanced CMOS technologies. This work proposes an effective methodology to aging analysis in flip-flops. The estimation method proposed previously for combinational logic gates is exploited and improved herein to address such sequential gates. Three different conventional static flip-flops have been used as case studies to demonstrate and validate the proposed methodology.