Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644888
SungHa Jung, M. Lim, Yi-hu Xu, Dae Hyun Jo
It is necessary to devise the efficient IFFT/FFT algorithm which can reduce computational complexity due to multiplication in the butterfly structure with twiddle factors in the OFDM based Cognitive Radio, where zero valued inputs/outputs outnumber nonzero inputs/outputs. Transformed Decomposition is considered as more suitable candidate than FFT pruning method for OFDM based Cognitive Radio due to the feasibility of HW design about irregular position of zero inputs/outputs in spite of more computation complexity than normal FFT pruning. However, with the introduction of the efficient control circuit for the pruning matrix which selects the multiplication branch with regular design corresponding to nonzero outputs in OFDM based cognitive radio, the split-radix FFT pruning algorithm can be proposed for getting more reduction of computational complexity. Through analyzing and comparing the computation complexity of the split-radix FFT pruning algorithm with other algorithms, it is shown that the proposed method is more efficient than other conventional algorithms. Based on the above mentioned design idea, the ASIC chip with 64-point split-radix FFT pruning was implemented using Samsung STD150E library.
{"title":"Implementation of split-radix FFT pruning for the reduction of computational complexity in OFDM based cognitive radio system","authors":"SungHa Jung, M. Lim, Yi-hu Xu, Dae Hyun Jo","doi":"10.1109/SBCCI.2013.6644888","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644888","url":null,"abstract":"It is necessary to devise the efficient IFFT/FFT algorithm which can reduce computational complexity due to multiplication in the butterfly structure with twiddle factors in the OFDM based Cognitive Radio, where zero valued inputs/outputs outnumber nonzero inputs/outputs. Transformed Decomposition is considered as more suitable candidate than FFT pruning method for OFDM based Cognitive Radio due to the feasibility of HW design about irregular position of zero inputs/outputs in spite of more computation complexity than normal FFT pruning. However, with the introduction of the efficient control circuit for the pruning matrix which selects the multiplication branch with regular design corresponding to nonzero outputs in OFDM based cognitive radio, the split-radix FFT pruning algorithm can be proposed for getting more reduction of computational complexity. Through analyzing and comparing the computation complexity of the split-radix FFT pruning algorithm with other algorithms, it is shown that the proposed method is more efficient than other conventional algorithms. Based on the above mentioned design idea, the ASIC chip with 64-point split-radix FFT pruning was implemented using Samsung STD150E library.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116748189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644881
R. Conceição, J. Cláudio, Souza Jr, R. Jeske, M. Porto, J. Mattos, L. Agostini
This paper is focused in the inverse transforms defined in the video coding standard HEVC - High Efficiency Video Coding. The transforms stage is one of the innovations proposed by HEVC since it allows the use of the biggest number of transforms sizes (four) and also the biggest transform sizes (till 32×32) when compared with previous standards. The inverse DCT is performed by the video encoder and decoder as well. This paper presents an efficient hardware design for the 32×32 HEVC IDCT based on the separability principle. The hardware design was planned to reach real time processing (at least 30 frames per second) for high resolution videos, exploiting a high parallelism level (32 samples consumed per clock cycle). The architecture was also planned to reach a low latency and a low cost, then it was designed in a purely combinational way and using a multiplierless approach. The synthesis process was targeted to an Altera Stratix IV FPGA. The synthesis results show that the designed architecture is capable to process more than 30 QFHD frames (3840×2160 pixels) per second, with a latency of 33 clock cycles.
本文主要研究视频编码标准HEVC (High Efficiency video coding)中定义的逆变换。转换阶段是HEVC提出的创新之一，因为与以前的标准相比，它允许使用最大数量的转换尺寸(四个)和最大的转换尺寸(直到32×32)。反向DCT由视频编码器和解码器完成。本文提出了一种基于可分性原理的32×32 HEVC IDCT的高效硬件设计方法。硬件设计计划达到高分辨率视频的实时处理(至少每秒30帧)，利用高并行性水平(每个时钟周期消耗32个样本)。该架构还计划达到低延迟和低成本，然后以纯粹的组合方式设计，并使用无乘法器方法。合成过程针对Altera Stratix IV FPGA。综合结果表明，所设计的架构能够每秒处理超过30个QFHD帧(3840×2160像素)，延迟为33个时钟周期。
{"title":"Hardware design for the 32×32 IDCT of the HEVC video coding standard","authors":"R. Conceição, J. Cláudio, Souza Jr, R. Jeske, M. Porto, J. Mattos, L. Agostini","doi":"10.1109/SBCCI.2013.6644881","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644881","url":null,"abstract":"This paper is focused in the inverse transforms defined in the video coding standard HEVC - High Efficiency Video Coding. The transforms stage is one of the innovations proposed by HEVC since it allows the use of the biggest number of transforms sizes (four) and also the biggest transform sizes (till 32×32) when compared with previous standards. The inverse DCT is performed by the video encoder and decoder as well. This paper presents an efficient hardware design for the 32×32 HEVC IDCT based on the separability principle. The hardware design was planned to reach real time processing (at least 30 frames per second) for high resolution videos, exploiting a high parallelism level (32 samples consumed per clock cycle). The architecture was also planned to reach a low latency and a low cost, then it was designed in a purely combinational way and using a multiplierless approach. The synthesis process was targeted to an Altera Stratix IV FPGA. The synthesis results show that the designed architecture is capable to process more than 30 QFHD frames (3840×2160 pixels) per second, with a latency of 33 clock cycles.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129603606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644861
G. Martins, F. Sousa
An RF-powered temperature sensor with power management and communication circuits designed with a standard 130 nm CMOS technology is reported. The system was designed to have an RFID-like functionality, i.e., the device communicates with an external reader, receiving power and backscattering information. Initially, the system collects energy in a low-power charging mode, with a rectifier optimally designed to operate with signal levels as low as -10 dBm centered approximately 900 MHz. Operating at condition of minimum input power, the system takes around 70 μs to power up. A calibration method was designed to enable a measurement error of less than 0.1°C while the sensor operates in the human body temperature range (35 to 42 °C). The circuits were simulated in the Cadence Spectre environment and the total power consumption observed was approximately 8.5μW when in active mode and 4.9μW when in standby mode. Some parts of the circuit were measured and preliminary results are reported.
{"title":"An RF-powered temperature sensor designed for biomedical applications","authors":"G. Martins, F. Sousa","doi":"10.1109/SBCCI.2013.6644861","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644861","url":null,"abstract":"An RF-powered temperature sensor with power management and communication circuits designed with a standard 130 nm CMOS technology is reported. The system was designed to have an RFID-like functionality, i.e., the device communicates with an external reader, receiving power and backscattering information. Initially, the system collects energy in a low-power charging mode, with a rectifier optimally designed to operate with signal levels as low as -10 dBm centered approximately 900 MHz. Operating at condition of minimum input power, the system takes around 70 μs to power up. A calibration method was designed to enable a measurement error of less than 0.1°C while the sensor operates in the human body temperature range (35 to 42 °C). The circuits were simulated in the Cadence Spectre environment and the total power consumption observed was approximately 8.5μW when in active mode and 4.9μW when in standby mode. Some parts of the circuit were measured and preliminary results are reported.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"167 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124660835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644884
Kleber Stangherlin, S. Bampi
Minimum-energy operation of digital CMOS circuits is commonly associated to the sub-VT regime, carrying huge performance and variability penalties. This paper shows that it is possible to achieve 8x higher energy-efficiency with a very-wide range of dynamic voltage-frequency scaling, from nominal voltages down to the lower boundary of near-VT operation. The cell-library is exercised in a 65nm commercial PDK and targets near-VT operation, mitigating the variability effects without compromising the design in terms of area and energy at strong inversion. The set of cells allows a maximum of 2-stacked transistors, and includes master-slave registers. We report results for medium complexity designs which include a 25kgates notch filter, a 20kgates 8051 compatible core, and 4-combinational/4-sequential ISCAS benchmark circuits. In this work the maximum frequency attainable at each supply for a wide variation of voltage is studied from 150mV up to nominal voltage (1.2V). The sub-VT operation is shown to hold the minimum energy-point at roughly 0.29V, which represents a 2x energy-saving compared to the near-VT regime. Although energy-efficiency peaks in sub-VT for the circuits studied, we also show that in this ultra-low Vdd the circuit timing and power suffer from substantially increased variability impact and a 30x performance drawback, with respect to near-VT.
{"title":"Energy-speed exploration for very-wide range of dynamic V-F scaling","authors":"Kleber Stangherlin, S. Bampi","doi":"10.1109/SBCCI.2013.6644884","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644884","url":null,"abstract":"Minimum-energy operation of digital CMOS circuits is commonly associated to the sub-VT regime, carrying huge performance and variability penalties. This paper shows that it is possible to achieve 8x higher energy-efficiency with a very-wide range of dynamic voltage-frequency scaling, from nominal voltages down to the lower boundary of near-VT operation. The cell-library is exercised in a 65nm commercial PDK and targets near-VT operation, mitigating the variability effects without compromising the design in terms of area and energy at strong inversion. The set of cells allows a maximum of 2-stacked transistors, and includes master-slave registers. We report results for medium complexity designs which include a 25kgates notch filter, a 20kgates 8051 compatible core, and 4-combinational/4-sequential ISCAS benchmark circuits. In this work the maximum frequency attainable at each supply for a wide variation of voltage is studied from 150mV up to nominal voltage (1.2V). The sub-VT operation is shown to hold the minimum energy-point at roughly 0.29V, which represents a 2x energy-saving compared to the near-VT regime. Although energy-efficiency peaks in sub-VT for the circuits studied, we also show that in this ultra-low Vdd the circuit timing and power suffer from substantially increased variability impact and a 30x performance drawback, with respect to near-VT.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131997988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644877
E. Costa, S. Almeida, Mônica Matzenauer
This paper proposes the implementation of dedicated hardware architecture for the Least Mean Square (LMS) adaptive filtering algorithm by using Gray encoding arithmetic operators, whose main goal is to cancel the interferences in the signal of interest. In the used scheme, from a 60Hz reference signal, the algorithm is able to estimate the superior harmonics, using after these results for the cancelling of interferences related to the signal of interest. One of most widely used technique for the switching activity reduction uses signal encoding. In this work, the proposed adaptive filtering architecture uses a Hybrid encoding in its data buses, which is a compromise between the minimal input dependency presented by the Binary encoding and the low switching characteristic of the Gray encoding. The main results showed that the Hybrid multipliers are more efficient than the Binary ones, by presenting less power consumption in some cases. Moreover, the implemented adaptive filtering architectures were validated and compared in both Binary and Hybrid encoding. The efficiency of the implemented Hybrid filter for the cancelling of interferences was proved by reducing more power than the Binary one. By the results, we conclude that it could be practicable to implement an adaptive filtering architecture operating on Hybrid encoding.
{"title":"Gray encoded fixed-point LMS adaptive filter architecture for the harmonics power line interference cancelling","authors":"E. Costa, S. Almeida, Mônica Matzenauer","doi":"10.1109/SBCCI.2013.6644877","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644877","url":null,"abstract":"This paper proposes the implementation of dedicated hardware architecture for the Least Mean Square (LMS) adaptive filtering algorithm by using Gray encoding arithmetic operators, whose main goal is to cancel the interferences in the signal of interest. In the used scheme, from a 60Hz reference signal, the algorithm is able to estimate the superior harmonics, using after these results for the cancelling of interferences related to the signal of interest. One of most widely used technique for the switching activity reduction uses signal encoding. In this work, the proposed adaptive filtering architecture uses a Hybrid encoding in its data buses, which is a compromise between the minimal input dependency presented by the Binary encoding and the low switching characteristic of the Gray encoding. The main results showed that the Hybrid multipliers are more efficient than the Binary ones, by presenting less power consumption in some cases. Moreover, the implemented adaptive filtering architectures were validated and compared in both Binary and Hybrid encoding. The efficiency of the implemented Hybrid filter for the cancelling of interferences was proved by reducing more power than the Binary one. By the results, we conclude that it could be practicable to implement an adaptive filtering architecture operating on Hybrid encoding.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125872625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644882
H. Klimach, A. L. T. Costa, M. F. C. Monteiro, S. Bampi
This work presents a novel Switched-capacitor Bandgap Voltage Reference (SCBGR) circuit that dispenses entirely the use of resistors. The vEB negative drift and the thermal voltage (VT) positive drift voltages are both generated by the same PNP vertical bipolar transistor, avoiding diode mismatch problems. The current sources that are used to generate different junction current densities are averaged in the switching process, reducing their mismatch impact on the circuit performance. A switched-capacitor circuit stores and processes these voltages, generating the bandgap reference voltage after 5 clock cycles. Since capacitors are used instead of resistors, variability problems like average process spread and device mismatches are reduced. The proposed topology was designed and simulated in CMOS for 180 nm process. This paper presents a systematic comparison to the traditional dual-BJT BGR and demonstrates the better performance of this new topology with respect to the former. Monte Carlo simulation shows significantly lower spread resulting from variations in the output reference voltage and in its temperature coefficient (TC).
{"title":"A resistorless switched bandgap voltage reference with offset cancellation","authors":"H. Klimach, A. L. T. Costa, M. F. C. Monteiro, S. Bampi","doi":"10.1109/SBCCI.2013.6644882","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644882","url":null,"abstract":"This work presents a novel Switched-capacitor Bandgap Voltage Reference (SCBGR) circuit that dispenses entirely the use of resistors. The vEB negative drift and the thermal voltage (VT) positive drift voltages are both generated by the same PNP vertical bipolar transistor, avoiding diode mismatch problems. The current sources that are used to generate different junction current densities are averaged in the switching process, reducing their mismatch impact on the circuit performance. A switched-capacitor circuit stores and processes these voltages, generating the bandgap reference voltage after 5 clock cycles. Since capacitors are used instead of resistors, variability problems like average process spread and device mismatches are reduced. The proposed topology was designed and simulated in CMOS for 180 nm process. This paper presents a systematic comparison to the traditional dual-BJT BGR and demonstrates the better performance of this new topology with respect to the former. Monte Carlo simulation shows significantly lower spread resulting from variations in the output reference voltage and in its temperature coefficient (TC).","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130569013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644860
Cicero Nunes, P. Butzen, A. Reis, R. Ribas
The impact of aging effects, in terms of circuit performance and reliability, is one of the new recent challenges in VLSI design targeting the most advanced CMOS technologies. This work proposes an effective methodology to aging analysis in flip-flops. The estimation method proposed previously for combinational logic gates is exploited and improved herein to address such sequential gates. Three different conventional static flip-flops have been used as case studies to demonstrate and validate the proposed methodology.
{"title":"A methodology to evaluate the aging impact on flip-flops performance","authors":"Cicero Nunes, P. Butzen, A. Reis, R. Ribas","doi":"10.1109/SBCCI.2013.6644860","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644860","url":null,"abstract":"The impact of aging effects, in terms of circuit performance and reliability, is one of the new recent challenges in VLSI design targeting the most advanced CMOS technologies. This work proposes an effective methodology to aging analysis in flip-flops. The estimation method proposed previously for combinational logic gates is exploited and improved herein to address such sequential gates. Three different conventional static flip-flops have been used as case studies to demonstrate and validate the proposed methodology.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121497559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644854
V. Possani, V. Callegaro, A. Reis, Renato P. Ribas, F. Marques, L. Rosa
This paper presents an improvement in our previous methodology to generate efficient transistor networks. The proposed method applies graph-based optimizations and is capable to deliver series-parallel and non-series-parallel arrangements with reduced transistor count. The main feature of our methodology is the possibility to avoid greedy choices during the beginning of the optimization process. This property is associated to an edges compression technique that also contributes to minimize the bad effect of the greedy choices. Performed experiments have demonstrated the efficiency of this methodology when comparing to other available techniques.
{"title":"Improving the methodology to build non-series-parallel transistor arrangements","authors":"V. Possani, V. Callegaro, A. Reis, Renato P. Ribas, F. Marques, L. Rosa","doi":"10.1109/SBCCI.2013.6644854","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644854","url":null,"abstract":"This paper presents an improvement in our previous methodology to generate efficient transistor networks. The proposed method applies graph-based optimizations and is capable to deliver series-parallel and non-series-parallel arrangements with reduced transistor count. The main feature of our methodology is the possibility to avoid greedy choices during the beginning of the optimization process. This property is associated to an edges compression technique that also contributes to minimize the bad effect of the greedy choices. Performed experiments have demonstrated the efficiency of this methodology when comparing to other available techniques.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131216196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644868
F. P. Cortes, Guilherme Freitas, Henrique Luiz Andrade Pimentel, J. P. M. Brito, F. Chávez
Radio Frequency Identification (RFID) systems are widely used in a variety of tracking, security and tagging applications. In this context, passive low-frequency (LF) RFID systems have a large installed base, mostly used for animal tagging and supply chain applications. This paper presents a Low-Power/Low-Voltage analog front-end architecture (AFE) for such RFID systems, discussing the design and technology issues related with standard deep-submicron CMOS processes. The AFE converts the incoming AC power (134.2kHz) into DC power (1.2V) and internal references (570mV and 5nA) using low power design techniques in order to increase overall performance. An improved rectifier structure was designed using a half-wave voltage doubler topology with self-bias feedback, providing efficient rectification. A shunt regulator stage was proposed as a fundamental part of the AFE architecture, since it keeps the rectified voltage at 3V and generates the signal for demodulation for all power levels and process variations. Finally, a low-power/low-voltage PMU architecture was designed, containing a new reference voltage approach based on two NMOS transistors with different Vt's consuming 170nA (startup circuit included); a 5nA reference current based in SCM (Self Cascode Mosfet) structures; and a dual-mode capacitor-less voltage regulator consuming 400nA. In order to increase the yield of the system, the VI reference block passed through a yield optimization using the tool WiCkeD, which showed a block yield increase of 71.66%.
{"title":"Low-Power/Low-Voltage analog front-end for LF passive RFID tag systems","authors":"F. P. Cortes, Guilherme Freitas, Henrique Luiz Andrade Pimentel, J. P. M. Brito, F. Chávez","doi":"10.1109/SBCCI.2013.6644868","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644868","url":null,"abstract":"Radio Frequency Identification (RFID) systems are widely used in a variety of tracking, security and tagging applications. In this context, passive low-frequency (LF) RFID systems have a large installed base, mostly used for animal tagging and supply chain applications. This paper presents a Low-Power/Low-Voltage analog front-end architecture (AFE) for such RFID systems, discussing the design and technology issues related with standard deep-submicron CMOS processes. The AFE converts the incoming AC power (134.2kHz) into DC power (1.2V) and internal references (570mV and 5nA) using low power design techniques in order to increase overall performance. An improved rectifier structure was designed using a half-wave voltage doubler topology with self-bias feedback, providing efficient rectification. A shunt regulator stage was proposed as a fundamental part of the AFE architecture, since it keeps the rectified voltage at 3V and generates the signal for demodulation for all power levels and process variations. Finally, a low-power/low-voltage PMU architecture was designed, containing a new reference voltage approach based on two NMOS transistors with different Vt's consuming 170nA (startup circuit included); a 5nA reference current based in SCM (Self Cascode Mosfet) structures; and a dual-mode capacitor-less voltage regulator consuming 400nA. In order to increase the yield of the system, the VI reference block passed through a yield optimization using the tool WiCkeD, which showed a block yield increase of 71.66%.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128063255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644891
Y. Ghidini, Matheus T. Moreira, Lucas Brahm, T. Webber, Ney Laert Vilar Calazans, C. Marcon
Communication plays a crucial role in the design of high performance Multiprocessor Systems-on-Chip (MPSoC). Accordingly, Networks-on-Chip (NoC) have been successfully employed as a solution to deal with communication in complex MPSoCs. NoC-based architectures are characterized by various tradeoffs related to structural characteristics, performance specifications, and application demands. In new technologies, the relative values of wire delays and power consumption are increasing as the number of cores in 2D chips increase. The recent 3D IC technology applied to NoC architectures allows greater device integration and shorter interconnection links, which directly influences the communication performance. Through-Silicon Vias (TSVs) are used for the interconnection between vertical layers of a 3D IC. The drawback is that TSVs are usually very expensive in terms of silicon area, limiting their usage. This work explores the serialization of vertical links, employing a TSV multiplexing scheme for Lasio, a 3D mesh NoC. We implemented and analyzed the impact in network and application latency and in the occupancy of input buffers for a 4×4×4 mesh NoC with different multiplexing degrees, which imply different levels of TSV usage reduction and serialization. Results demonstrate that the proposed scheme allows reducing TSV usage with low performance overhead, pointing to potential benefits of the scheme in 3D NoC-based MPSoCs.
{"title":"Lasio 3D NoC vertical links serialization: Evaluation of latency and buffer occupancy","authors":"Y. Ghidini, Matheus T. Moreira, Lucas Brahm, T. Webber, Ney Laert Vilar Calazans, C. Marcon","doi":"10.1109/SBCCI.2013.6644891","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644891","url":null,"abstract":"Communication plays a crucial role in the design of high performance Multiprocessor Systems-on-Chip (MPSoC). Accordingly, Networks-on-Chip (NoC) have been successfully employed as a solution to deal with communication in complex MPSoCs. NoC-based architectures are characterized by various tradeoffs related to structural characteristics, performance specifications, and application demands. In new technologies, the relative values of wire delays and power consumption are increasing as the number of cores in 2D chips increase. The recent 3D IC technology applied to NoC architectures allows greater device integration and shorter interconnection links, which directly influences the communication performance. Through-Silicon Vias (TSVs) are used for the interconnection between vertical layers of a 3D IC. The drawback is that TSVs are usually very expensive in terms of silicon area, limiting their usage. This work explores the serialization of vertical links, employing a TSV multiplexing scheme for Lasio, a 3D mesh NoC. We implemented and analyzed the impact in network and application latency and in the occupancy of input buffers for a 4×4×4 mesh NoC with different multiplexing degrees, which imply different levels of TSV usage reduction and serialization. Results demonstrate that the proposed scheme allows reducing TSV usage with low performance overhead, pointing to potential benefits of the scheme in 3D NoC-based MPSoCs.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"9 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126040948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：