Folded bit-plane FIR filter architecture with changeable folding factor

Abstract

The application of folding technique to the bit-plane systolic FIR filter architecture that enables the implementation of changeable folding factor onto the fixed size array is described in this paper. The transformation of original data flow graph (DFG) for bit-plane architecture that provides the successful application of the folding technique with changeable folding sets is presented. The involving of changeable folding sets in the synthesized folded architecture allows the reducing of folding factor according to the coefficient length increasing the throughput of the folded system.