Hot Carrier Stress Investigation of Zinc Oxide Thin Film Transistors with an Al2O3 Gate Dielectric

Abstract

Hot carrier stress, where the gate and drain voltages were stressed simultaneously, was executed on ZnO thin-film transistors (TFTs) with different PLD ZnO or ALD Al2O3 deposition parameters. The threshold voltage and transconductance were monitored where 30 mTorr samples had greater threshold voltage shifts and transconductance $(\mathrm{g}_{\mathrm{m}})$ degradation compared to the 20 mTorr ZnO film. For samples with and without a 400°C forming gas anneal, greater degradation was seen in the annealed sample, which indicates 400°C may be too aggressive. The correlation between $\mathrm{g}_{\mathrm{m}}$ degradation (i.e., interface degradation) and $\Delta \mathrm{V}_{\mathrm{t}}$ demonstrate that there is influence to the Vt shift from electrically active defects generated in the interfacial region.