Ge deep sub-micron pFETs with etched TaN metal gate on a high-k dielectric, fabricated in a 200mm silicon prototyping line

Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI:10.1109/ESSDER.2004.1356521

B. de Jaeger, M. Houssa, A. Satta, S. Kubicek, P. Verheyen, J. Van Steenbergen, J. Croon, B. Kaczer, S. Van Elshocht, A. Delabie, E. Kunnen, E. Sleeckx, I. Teerlinck, R. Lindsay, T. Schram, T. Chiarella, R. Degraeve, T. Conard, J. Poortmans, G. Winderickx, W. Boullart, M. Schaekers, P. Mertens, M. Caymax, W. Vandervorst, E. Van Moorhem, S. Biesemans, K. De Meyer, L. Ragnarsson, S. Lee, G. Kota, G. Raskin, P. Mijlemans, J. Autran, V. Afanas’ev, A. Stesmans, M. Meuris, M. Heyns

{"title":"Ge deep sub-micron pFETs with etched TaN metal gate on a high-k dielectric, fabricated in a 200mm silicon prototyping line","authors":"B. de Jaeger, M. Houssa, A. Satta, S. Kubicek, P. Verheyen, J. Van Steenbergen, J. Croon, B. Kaczer, S. Van Elshocht, A. Delabie, E. Kunnen, E. Sleeckx, I. Teerlinck, R. Lindsay, T. Schram, T. Chiarella, R. Degraeve, T. Conard, J. Poortmans, G. Winderickx, W. Boullart, M. Schaekers, P. Mertens, M. Caymax, W. Vandervorst, E. Van Moorhem, S. Biesemans, K. De Meyer, L. Ragnarsson, S. Lee, G. Kota, G. Raskin, P. Mijlemans, J. Autran, V. Afanas’ev, A. Stesmans, M. Meuris, M. Heyns","doi":"10.1109/ESSDER.2004.1356521","DOIUrl":null,"url":null,"abstract":"We report for the first time on deep sub-micron Ge pFETs with physical gate lengths down to 0.151 /spl mu/m. The devices are made using a silicon-like process flow, with a directly etched gate stack consisting of TaN gate on an ALD or MOCVD HfO/sub 2/ dielectric. Promising drive currents are found. Various issues such as the severe short channel effects (SCE), the increased diode leakage compared to Si and the high amount of interface states (N/sub it/) are addressed. The need for an alternative Ge substrate pre-treatment and subsequent high-k gate dielectric deposition to push EOT values below 1 nm is illustrated.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"2011 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDER.2004.1356521","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 11

Abstract

We report for the first time on deep sub-micron Ge pFETs with physical gate lengths down to 0.151 /spl mu/m. The devices are made using a silicon-like process flow, with a directly etched gate stack consisting of TaN gate on an ALD or MOCVD HfO/sub 2/ dielectric. Promising drive currents are found. Various issues such as the severe short channel effects (SCE), the increased diode leakage compared to Si and the high amount of interface states (N/sub it/) are addressed. The need for an alternative Ge substrate pre-treatment and subsequent high-k gate dielectric deposition to push EOT values below 1 nm is illustrated.

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在高k介电介质上蚀刻TaN金属栅极的Ge深亚微米pfet，在200mm硅原型生产线上制造

我们首次报道了深亚微米Ge pfet，其物理栅极长度降至0.151 /spl mu/m。该器件采用类硅工艺流程制造，在ALD或MOCVD HfO/sub /介电介质上直接蚀刻由TaN栅极组成的栅极堆栈。找到了有希望的驱动电流。解决了各种问题，例如严重的短通道效应(SCE)，与Si相比增加的二极管泄漏和大量的界面状态(N/sub / it/)。需要替代Ge衬底预处理和随后的高k栅极介电沉积，以将EOT值推至1 nm以下。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)

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