{"title":"A Fully Digital Low Cost Time Domain Smart Temperature Sensor with Extremely Tiny Size","authors":"Poki Chen, Mon-Chau Shie, Zi-Fan Zheng, C. Chu, Mao-Hsing Chiang, Zhi-Yuan Zheng","doi":"10.1109/ASSCC.2006.357873","DOIUrl":null,"url":null,"abstract":"To explore the possibility of soft IP implementation, a fully digital smart temperature sensor without any full-custom device is proposed for painless VLSI or SOC on-chip integrations. The signal is processed thoroughly in time domain instead of conventional voltage or current domain. A cyclic delay line is used to generate the thermally sensitive pulse with a width proportional to the measured temperature. The timing reference is just the input clock, and a counter instead of voltage or current analog-to-digital converter is utilized for digital output coding. The circuit is realized by FPGA chips for functionality verification and performance evaluation. Implemented with as few as 140 Logic Elements, the proposed smart sensor was measured to have an error of -0.7degC~0.9degC over a wide temperature range of -40degC~130degC. The effective resolution is better than 0.1degC, and the power consumption is 8.42 muW at a sample rate of 2 samples/s. The performance is as good as those of most full-custom predecessors. The longest conversion time is around 260 mus, and a conversion rate of 3 kHz at least is promised.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2006.357873","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
To explore the possibility of soft IP implementation, a fully digital smart temperature sensor without any full-custom device is proposed for painless VLSI or SOC on-chip integrations. The signal is processed thoroughly in time domain instead of conventional voltage or current domain. A cyclic delay line is used to generate the thermally sensitive pulse with a width proportional to the measured temperature. The timing reference is just the input clock, and a counter instead of voltage or current analog-to-digital converter is utilized for digital output coding. The circuit is realized by FPGA chips for functionality verification and performance evaluation. Implemented with as few as 140 Logic Elements, the proposed smart sensor was measured to have an error of -0.7degC~0.9degC over a wide temperature range of -40degC~130degC. The effective resolution is better than 0.1degC, and the power consumption is 8.42 muW at a sample rate of 2 samples/s. The performance is as good as those of most full-custom predecessors. The longest conversion time is around 260 mus, and a conversion rate of 3 kHz at least is promised.