Computing detection probability of delay defects in signal line tsvs

Abstract

Three-dimensional stacking technology promises to solve the interconnect bottleneck problem by using Through-Silicon-Vias (TSVs) to vertically connect circuit layers. However, manufacturing steps may lead to partly broken or incompletely filled TSVs that may degrade the performance and reduce the useful lifetime of a 3D IC. Due to combinations of physical factors such as switching activity, supply noise and crosstalk, path delays can experience speed-up or slow-down that could let the effect of resistive open TSV go undetected by conventional test methods. In this work, we present a metric based on probabilistic analysis to detect delay defects induced by resistive opens that occur on signal line TSVs. Our experimental result will show the accuracy of the proposed metric.