Scaling Beyond 7nm: Design-Technology Co-optimization at the Rescue

Abstract

At 7nm and beyond, designers need to support scaling by identifying the most optimal patterning schemes for their designs. Moreover, designers can actively help by exploring scaling options that do not necessarily require aggressive pitch scaling. In this talk we will illustrate how design technology co-optimization can help achieving the expected Moore's law scaling; how optimizing device performance can lead to smaller standard cells; how the metal interconnect stack needs to be adjusted for unidirectional metals and how a vertical transistor can shift design paradigms. This paper demonstrates that scaling has become a joint design-technology co-optimization effort between process technology and design specialists, that expands way beyond just patterning enabled dimensional scaling.