Rethinking programmable earable processors

Nathaniel Bleier, Muhammad Husnain Mubarik, Srijan Chakraborty, S. Kishore, Rakesh Kumar
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引用次数: 1

Abstract

Earables such as earphones [15, 16, 73], hearing aids [28], and smart glasses [2, 14] are poised to be a prominent programmable computing platform in the future. In this paper, we ask the question: what kind of programmable hardware would be needed to support earable computing in future? To understand hardware requirements, we propose EarBench, a suite of representative emerging earable applications with diverse sensor-based inputs and computation requirements. Our analysis of EarBench applications shows that, on average, there is a 13.54×-3.97× performance gap between the computational needs of EarBench applications and the performance of the microprocessors that several of today's programmable earable SoCs are based on; more complex microprocessors have unacceptable energy efficiency for Earable applications. Our analysis also shows that EarBench applications are dominated by a small number of digital signal processing (DSP) and machine learning (ML)-based kernels that have significant computational similarity. We propose SpEaC --- a coarse-grained reconfigurable spatial architecture - as an energy-efficient programmable processor for earable applications. SpEaC targets earable applications efficiently using a) a reconfigurable fixed-point multiply-and-add augmented reduction tree-based substrate with support for vectorized complex operations that is optimized for the earable ML and DSP kernel code and b) a tightly coupled control core for executing other code (including non-matrix computation, or non-multiply or add operations in the earable DSP kernel code). Unlike other CGRAs that typically target general-purpose computations, SpEaC substrate is optimized for energy-efficient execution of the earable kernels at the expense of generality. Across all our kernels, SpEaC outperforms programmable cores modeled after M4, M7, A53, and HiFi4 DSP by 99.3×, 32.5×, 14.8×, and 9.8× respectively. At 63 mW in 28 nm, the energy efficiency benefits are 1.55 ×, 9.04×, 68.3 ×, and 32.7 × respectively; energy efficiency benefits are 15.7 × -- 1087 × over a low power Mali T628 MP6 GPU.
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重新思考可编程耳式处理器
耳机[15,16,73]、助听器[28]和智能眼镜[2,14]等可穿戴设备将成为未来重要的可编程计算平台。在本文中,我们提出了这样一个问题:未来需要什么样的可编程硬件来支持可穿戴计算?为了了解硬件需求,我们提出了EarBench,这是一套具有不同传感器输入和计算需求的代表性新兴耳式应用程序。我们对EarBench应用程序的分析表明,平均而言,EarBench应用程序的计算需求与当今几种可编程耳式soc所基于的微处理器的性能之间存在13.54×-3.97×性能差距;更复杂的微处理器对于Earable应用具有不可接受的能源效率。我们的分析还表明,EarBench应用程序由少数具有显著计算相似性的基于数字信号处理(DSP)和机器学习(ML)的内核主导。我们提出SpEaC——一种粗粒度的可重构空间架构——作为可穿戴应用的节能可编程处理器。SpEaC有效地针对可耳应用,使用a)可重构的定点乘加增强约简树基板,支持针对可耳ML和DSP内核代码优化的矢量化复杂操作;b)用于执行其他代码(包括可耳DSP内核代码中的非矩阵计算或非乘法或加法操作)的紧密耦合控制核心。与其他通常针对通用计算的CGRAs不同,SpEaC基板以牺牲通用性为代价,优化了可听内核的节能执行。在我们所有的内核中,SpEaC的性能分别比M4、M7、A53和HiFi4 DSP的可编程内核高99.3倍、32.5倍、14.8倍和9.8倍。在28 nm、63 mW时,能效效益分别为1.55 ×、9.04×、68.3 ×和32.7 ×;与低功耗Mali T628 MP6 GPU相比,能效优势为15.7 ×—1087 ×。
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