C4: An FPGA-based Compression Algorithm for ExpEther

Abstract

PCI Express (PCIe) has been widely used as an I/O bus connecting CPU and GPUs. In order to resolve the limitation of the number of PCIe ports, NEC Corporation developed ExpEther for expanding PCIe to Ethernet. Since Ethernet often becomes a bottleneck of communication, a conventional research proposed to implement a compression/decompression mechanism by using existing data compression mechanisms to reduce the size of data transferring on Ethernet. However, data compression mechanisms used in the research were only efficient for a limited input data pattern. In this paper, we proposed a novel data compression algorithm called C4, and implemented it on Xilinx Virtex-7 FPGA as an experimental environment of ExpEther. As a result, the proposed method can reduce the transfer time by 52.5%, superior to 49.7% with the conventional method. According to the evaluation of the hardware resource utilization rate, we showed that the proposed algorithm can be implemented in the FPGA used in the ExpEther NIC.