A. Romariz, P. Ferreira, J. Campêlo, M. L. Graciano, J. C. Costa
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引用次数: 4
Abstract
A hybrid architecture for neural coprocessing is presented. A fixed set of analog multipliers and capacitors (analog memory) emulates multilayer perceptrons through digitally-controlled multiplexing. Thus parallelism is partially preserved without direct analog implementation of the whole structure. Details of system VLSI implementation are given, along with simulation results and performance estimation.
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