Y. Kawano, A. Mineyama, Toshihide Suzuki, Masaru Sato, T. Hirose, K. Joshin
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引用次数: 26
Abstract
A fully-integrated K-band differential power amplifier was designed in 65 nm CMOS. The power amplifier comprised of the 2-stage cascode configuration has the matching networks based on the transformer. To match the impedances, turn ratios of each transformer were designed to be 1∶1 for the input stage, 2∶1 for the inter stage, and 1∶1.5 for the output stage, respectively. The saturation power of more than 20 dBm was obtained in the band between 16 GHz and 25 GHz. The peak value of the saturation power was 23.8 dBm, and the power added efficiency (PAE) was 25.1 % at 19 GHz. The chip occupied area including the DC and RF pads is 1.2 × 0.8 mm.
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