Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940673
Hua Wang, K. Dasgupta, A. Hajimiri
This paper presents a full-range broadband phase synthesis scheme with autonomous phase correction functionality. The on-chip phase measurement is achieved by a set of on-chip LO self-/inter-mixing testing sequences, which eliminates the need for auxiliary test tones. As a design example, a 2-to-6GHz quadrature phase synthesis system in a 65nm CMOS is demonstrated. The phase self-healing scheme achieves an RMS phase error of less than 0.6° and a full 360° interpolation within the entire band.
{"title":"A broadband self-healing phase synthesis scheme","authors":"Hua Wang, K. Dasgupta, A. Hajimiri","doi":"10.1109/RFIC.2011.5940673","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940673","url":null,"abstract":"This paper presents a full-range broadband phase synthesis scheme with autonomous phase correction functionality. The on-chip phase measurement is achieved by a set of on-chip LO self-/inter-mixing testing sequences, which eliminates the need for auxiliary test tones. As a design example, a 2-to-6GHz quadrature phase synthesis system in a 65nm CMOS is demonstrated. The phase self-healing scheme achieves an RMS phase error of less than 0.6° and a full 360° interpolation within the entire band.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115117610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940631
Fu-Kang Wang, Chi-Tsan Chen, Jiun-Ru Tsai, T. Horng, K. Peng, J. Jau, Jian-Yu Li, Cheng‐Chung Chen
This paper presents a CMOS spectrum sensor to detect spectral usage and spectrum holes for cognitive radio system. The sensor mainly consists of a swept oscillator and a frequency discriminator, both of which use the injection locking of voltage-controlled oscillator (VCO) to process the sensed signal without requiring a frequency synthesizer. As a demonstration, the sensor is designed to operate in the 2.4 GHz industrial-scientific-medical (ISM) band and implemented using 0.18 µm CMOS technology. It can detect the frequency and power for wireless communication signals with high accuracy at a spectrum scanning speed of 100 MHz/ms. The sensitivity can be below −100 dBm when an external low-noise amplifier (LNA) is used in front of the sensor IC.
{"title":"A CMOS spectrum sensor using injection locking of two voltage-controlled oscillators for cognitive radio system","authors":"Fu-Kang Wang, Chi-Tsan Chen, Jiun-Ru Tsai, T. Horng, K. Peng, J. Jau, Jian-Yu Li, Cheng‐Chung Chen","doi":"10.1109/RFIC.2011.5940631","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940631","url":null,"abstract":"This paper presents a CMOS spectrum sensor to detect spectral usage and spectrum holes for cognitive radio system. The sensor mainly consists of a swept oscillator and a frequency discriminator, both of which use the injection locking of voltage-controlled oscillator (VCO) to process the sensed signal without requiring a frequency synthesizer. As a demonstration, the sensor is designed to operate in the 2.4 GHz industrial-scientific-medical (ISM) band and implemented using 0.18 µm CMOS technology. It can detect the frequency and power for wireless communication signals with high accuracy at a spectrum scanning speed of 100 MHz/ms. The sensitivity can be below −100 dBm when an external low-noise amplifier (LNA) is used in front of the sensor IC.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115434700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940612
Yun-A Shim, S. Yuwono, Seung-Jin Kim, Joo-Myoung Kim, Seok-Kyun Han, Sang-Gug Lee, D. Ha
This paper presents a low power, low complexity IR-UWB radar transceiver for short range object detection. The transceiver provides robustness against false alarms without increasing power consumption, chip size, or complexity. The receiver (RX) and the transmitter (TX) dissipate only 50 pJ/pulse and 470 pJ/pulse under a 1.2V supply, respectively. The measured TX pulse spectrum, −58 dBm maximum power, complies with the FCC spectral mask and shows 1 GHz bandwidth with 4 GHz center frequency. The measured sensitivity of the RX is −45 dBm, and the RX is fully functional to detect an object in the range of 0.45 ∼ 1.2 m. The die size of the IR-UWB transceiver implemented in a 0.13 um CMOS process is 2.1 mm2.
{"title":"A 520 pJ/pulse IR-UWB radar for short range object detection","authors":"Yun-A Shim, S. Yuwono, Seung-Jin Kim, Joo-Myoung Kim, Seok-Kyun Han, Sang-Gug Lee, D. Ha","doi":"10.1109/RFIC.2011.5940612","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940612","url":null,"abstract":"This paper presents a low power, low complexity IR-UWB radar transceiver for short range object detection. The transceiver provides robustness against false alarms without increasing power consumption, chip size, or complexity. The receiver (RX) and the transmitter (TX) dissipate only 50 pJ/pulse and 470 pJ/pulse under a 1.2V supply, respectively. The measured TX pulse spectrum, −58 dBm maximum power, complies with the FCC spectral mask and shows 1 GHz bandwidth with 4 GHz center frequency. The measured sensitivity of the RX is −45 dBm, and the RX is fully functional to detect an object in the range of 0.45 ∼ 1.2 m. The die size of the IR-UWB transceiver implemented in a 0.13 um CMOS process is 2.1 mm2.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"265 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123044179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940625
Monte K. Watanabe, T. LaRocca
The first known GaN implementation of high-power digital controlled artificial dielectric (DiCAD) reconfigurable transmission lines is presented. DiCAD was formed by integrating GaN HEMT switches and metal-insulator-metal capacitors (MIMCAPs) into coplanar strip transmission lines. Standard GaN HEMT processing techniques were used, making DiCAD easily compatible with future circuit designs. The DiCAD transmission line's effective dielectric constant exhibits linear digital control from 15 to 32 with 3-bit resolution up to 50GHz. P1dB is measured to be greater than 27dBm and OIP3 is calculated to be greater than 48dBm for all states.
{"title":"High-power digital controlled artificial dielectric GaN reconfigurable transmission lines for digitally assisted RFICs","authors":"Monte K. Watanabe, T. LaRocca","doi":"10.1109/RFIC.2011.5940625","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940625","url":null,"abstract":"The first known GaN implementation of high-power digital controlled artificial dielectric (DiCAD) reconfigurable transmission lines is presented. DiCAD was formed by integrating GaN HEMT switches and metal-insulator-metal capacitors (MIMCAPs) into coplanar strip transmission lines. Standard GaN HEMT processing techniques were used, making DiCAD easily compatible with future circuit designs. The DiCAD transmission line's effective dielectric constant exhibits linear digital control from 15 to 32 with 3-bit resolution up to 50GHz. P1dB is measured to be greater than 27dBm and OIP3 is calculated to be greater than 48dBm for all states.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"391 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116647525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940690
M. Abbasi, T. Kjellberg, A. de Graauw, R. Roovers, H. Zirath
A compact 60 GHz direct conversion quadrature transmitter is designed and fabricated in 45 nm standard LP CMOS. The transmitter features an integrated power amplifier with continuous output level control and interfaces binary data signals with nominal peak-to-peak voltage swing of 300 mV. The highest measured modulation bandwidth is limited by the measurement setup to 4 GHz but is simulated to be as high as 10 GHz. In single sideband up-converting operation mode, the measured image suppression ratio is 22 dB with 36 dB of carrier suppression corresponding to approximately 8% EVM in the output signal constellation. The output RF frequency can be from 54 GHz to 66 GHz to accommodate several channels and the output power can be adjusted from −3 dBm to 10 dBm. The chip is operated from a 2 V supply and draws 180 mA current.
{"title":"A direct conversion quadrature transmitter with digital interface in 45 nm CMOS for high-speed 60 GHz communications","authors":"M. Abbasi, T. Kjellberg, A. de Graauw, R. Roovers, H. Zirath","doi":"10.1109/RFIC.2011.5940690","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940690","url":null,"abstract":"A compact 60 GHz direct conversion quadrature transmitter is designed and fabricated in 45 nm standard LP CMOS. The transmitter features an integrated power amplifier with continuous output level control and interfaces binary data signals with nominal peak-to-peak voltage swing of 300 mV. The highest measured modulation bandwidth is limited by the measurement setup to 4 GHz but is simulated to be as high as 10 GHz. In single sideband up-converting operation mode, the measured image suppression ratio is 22 dB with 36 dB of carrier suppression corresponding to approximately 8% EVM in the output signal constellation. The output RF frequency can be from 54 GHz to 66 GHz to accommodate several channels and the output power can be adjusted from −3 dBm to 10 dBm. The chip is operated from a 2 V supply and draws 180 mA current.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117108095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940647
U. Gogineni, J. D. del Alamo, A. Valdes-Garcia
This paper presents a first order model for RF power of deeply scaled CMOS. The model highlights the role of device on-resistance in determining the maximum RF power. We show excellent agreement between the model and the measured data on 45 nm CMOS devices across a wide range of device widths, under both maximum output power and maximum PAE conditions. The model allows circuit designers to quickly estimate the power and efficiency of a device layout without need for complicated compact models or simulations.
{"title":"Analytical model for RF power performance of deeply scaled CMOS devices","authors":"U. Gogineni, J. D. del Alamo, A. Valdes-Garcia","doi":"10.1109/RFIC.2011.5940647","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940647","url":null,"abstract":"This paper presents a first order model for RF power of deeply scaled CMOS. The model highlights the role of device on-resistance in determining the maximum RF power. We show excellent agreement between the model and the measured data on 45 nm CMOS devices across a wide range of device widths, under both maximum output power and maximum PAE conditions. The model allows circuit designers to quickly estimate the power and efficiency of a device layout without need for complicated compact models or simulations.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125832310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940621
M. Kwak, D. Kimball, C. Presti, A. Scuderi, C. Santagati, Jonmei J. Yan, P. Asbeck, L. Larson
This paper presents a high performance BCD (Bipolar-CMOS-DMOS) monolithic envelope tracking IC to achieve high efficiency and linearity for micro-base station power amplifier applications. Measurement of the BCD high voltage (Vdd = 15 V) envelope amplifier shows an efficiency of 72% using WCDMA input signals (7.7 dB PAR). An envelope tracking power amplifier including a GaN FET RF stage has overall drain efficiency (DE) above 51%, with a normalized power RMS error below 1.2% and ACLR1 of −49 dBc using memory mitigation digital pre-distortion (DPD), at an average WCDMA output power above 2 W and a gain of 10 dB.
本文提出了一种高性能BCD(双极cmos - dmos)单片包络跟踪集成电路，用于微基站功率放大器，实现了高效率和线性度。BCD高压(Vdd = 15 V)包络放大器的测量表明，使用WCDMA输入信号(7.7 dB PAR)，效率为72%。在WCDMA平均输出功率大于2w，增益为10db的情况下，包含GaN场效应管射频级的包线跟踪功率放大器总体漏极效率(DE)高于51%，采用内存缓解数字预失真(DPD)，归一化功率均方根误差低于1.2%，ACLR1为- 49 dBc。
{"title":"Wideband high efficiency envelope tracking integrated circuit for micro-base station power amplifiers","authors":"M. Kwak, D. Kimball, C. Presti, A. Scuderi, C. Santagati, Jonmei J. Yan, P. Asbeck, L. Larson","doi":"10.1109/RFIC.2011.5940621","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940621","url":null,"abstract":"This paper presents a high performance BCD (Bipolar-CMOS-DMOS) monolithic envelope tracking IC to achieve high efficiency and linearity for micro-base station power amplifier applications. Measurement of the BCD high voltage (Vdd = 15 V) envelope amplifier shows an efficiency of 72% using WCDMA input signals (7.7 dB PAR). An envelope tracking power amplifier including a GaN FET RF stage has overall drain efficiency (DE) above 51%, with a normalized power RMS error below 1.2% and ACLR1 of −49 dBc using memory mitigation digital pre-distortion (DPD), at an average WCDMA output power above 2 W and a gain of 10 dB.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115219460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940604
E. Ojefors, B. Heinemann, U. Pfeiffer
A monolithic 220-GHz receiver front-end manufactured in an engineering version of an ƒT /ƒmax = 280/435-GHz SiGe technology is presented. The front-end consists of a three-stage differential LNA and a subharmonic mixer. A breakout of the 220-GHz LNA provides 15 dB gain and a bandwidth of 28 GHz. The integrated downconverter yields a conversion gain of 16 dB, a 15-dB DSB NF, and a 30-GHz bandwidth when pumped with a 0-dBm, 110-GHz LO signal.
{"title":"A 220GHz subharmonic receiver front end in a SiGe HBT technology","authors":"E. Ojefors, B. Heinemann, U. Pfeiffer","doi":"10.1109/RFIC.2011.5940604","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940604","url":null,"abstract":"A monolithic 220-GHz receiver front-end manufactured in an engineering version of an ƒT /ƒmax = 280/435-GHz SiGe technology is presented. The front-end consists of a three-stage differential LNA and a subharmonic mixer. A breakout of the 220-GHz LNA provides 15 dB gain and a bandwidth of 28 GHz. The integrated downconverter yields a conversion gain of 16 dB, a 15-dB DSB NF, and a 30-GHz bandwidth when pumped with a 0-dBm, 110-GHz LO signal.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114282323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940697
M. Lont, D. Milosevic, A. Roermund, G. Dolmans
In this paper, we present an ultra low-power Wake-up Receiver front-end operating in the 868/915MHz ISM band. It targets short distance body area networks. Its power consumption is only 126uW, including a low-power on-chip ring oscillator. Since the receiver targets small transmission distances, up to 10m, sensitivity is traded against power consumption. This is achieved by removing the LNA and making all the gain at the low IF frequencies. The receiver sensitivity is −65dBm at a BER of 0.1%.
{"title":"Ultra-low power FSK Wake-up Receiver front-end for body area networks","authors":"M. Lont, D. Milosevic, A. Roermund, G. Dolmans","doi":"10.1109/RFIC.2011.5940697","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940697","url":null,"abstract":"In this paper, we present an ultra low-power Wake-up Receiver front-end operating in the 868/915MHz ISM band. It targets short distance body area networks. Its power consumption is only 126uW, including a low-power on-chip ring oscillator. Since the receiver targets small transmission distances, up to 10m, sensitivity is traded against power consumption. This is achieved by removing the LNA and making all the gain at the low IF frequencies. The receiver sensitivity is −65dBm at a BER of 0.1%.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117238360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940654
T. Nakatani, J. Rode, D. Kimball, L. Larson, P. Asbeck
A digital polar transmitter with a watt-class CMOS power amplifier is demonstrated, implemented with a 0.15um RF CMOS process. Current-mode class-D configuration and stacked FETs are used to obtain high efficiency and high breakdown voltage in the output stage, which was measured to have 31 dBm output power with 51% drain efficiency under single tone testing. The output stage is fed by a buck converter employing digital pulse width modulation with 47 MHz pulse rate synchronized with a 3 GHz clock. Digital compensation techniques were developed to maintain linearity. WCDMA HPSK modulation was demonstrated using a pulse pattern generator-based measurement bench. Overall efficiency of 26.5 % efficiency was achieved while maintaining ACLRs within 3GPP specifications at 24 dBm average output power.
{"title":"Digital polar transmitter using a watt-class current-mode class-D CMOS power amplifier","authors":"T. Nakatani, J. Rode, D. Kimball, L. Larson, P. Asbeck","doi":"10.1109/RFIC.2011.5940654","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940654","url":null,"abstract":"A digital polar transmitter with a watt-class CMOS power amplifier is demonstrated, implemented with a 0.15um RF CMOS process. Current-mode class-D configuration and stacked FETs are used to obtain high efficiency and high breakdown voltage in the output stage, which was measured to have 31 dBm output power with 51% drain efficiency under single tone testing. The output stage is fed by a buck converter employing digital pulse width modulation with 47 MHz pulse rate synchronized with a 3 GHz clock. Digital compensation techniques were developed to maintain linearity. WCDMA HPSK modulation was demonstrated using a pulse pattern generator-based measurement bench. Overall efficiency of 26.5 % efficiency was achieved while maintaining ACLRs within 3GPP specifications at 24 dBm average output power.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128276789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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