An Over-Erasure Detection Technique for Tightening Vth Distribution for Low Voltage Operation Nor Type Flash Memory

Abstract

Introduction Recent development of hand-held digital equipment demands a low voltage operation non-volatile memory. Already a 3.3-V operation 16-Mb flash memories have been reported [1][2], and word line boost schemes have been shown to be very effective in lowering operational voltage[2][3]. Further Vcc reduction by word line boosting, however, increases power consumption and access time. Lowering the threshold voltage in the erased state becomes inevitable, which induces an over-erasure problem if the fluctuation of memory cell characteristics is large. If the detection of over-erased bits can be performed, the threshold voltage distribution can be tightened by an over-erasure recovery procedure such as bit-by-bit "1" programming. This paper describes a source line bias scheme and the supply voltage shifting of a sense amplifier for over-erased bit detection without a negative voltage and chip area penalty.