Integrating assertion-based verification into system-level synthesis methodology

Abstract

In this paper, we integrate a verification methodology with our object-oriented system-level synthesis methodology to address the problem of HW/SW co-verification after system synthesis. We have defined a set of system-level assertions. These assertions are automatically converted to monitor hardware or monitor software during the system-level synthesis process depending on their type and also synthesis style of their corresponding functions. The synthesized assertions are functionally equivalent to their original system-level assertion, and hence, can he used to verify the system after HW/SW synthesis. This way, not only system-level assertions are reused in lower-levels of abstraction, but also run-time verification of system is provided. In this paper, we show the system-level assertions and their synthesis method in our object-oriented system-level synthesis methodology.