A high throughput sort free VLSI architecture for wireless applications

Abstract

For high data rate Multiple Input Multiple Output technology is used in wireless communications. The use of multiple antennas at both transmitter and receiver (MIMO) significantly increases the capacity and spectral efficiency of wireless systems. This paper presents a Field Programmable Gate Array (FPGA) implementation for a 4 × 4 breadth first K-best MIMO decoder using a 64 Quadrature Amplitude Modulation (QAM) scheme. A novel sort free approach to path extension, as well as, quantized metrics result in a high throughput, low power and area. Finally, VLSI architectural tradeoffs are explored for a synthesized using synopsys the power analysis, throughput analysis in 120 nm technology. The power needed is 20.0025 μW.