{"title":"Predictive analysis of sensitivity to chip-routing parasitics","authors":"R. Melville, A. Yiannoulos","doi":"10.1109/ASIC.1989.123245","DOIUrl":null,"url":null,"abstract":"The authors describe a system which is able automatically to bring to the attention of the designer significant performance sensitivities which are introduced through interconnection parasitics. The input to the tool is a SPICE file and a performance specification provided by a designer. The output is again a SPICE file, but augmented with those interconnection parasitics which are most significant for the performance specification prescribed by the designer. The value attached to a parasitic is a quantitative estimate of how significant the parasitic is. This information is derived from a simulation of the circuit prior to layout. The list of most significant routing parasitics could be used to provide feedback to a human designer, direct an automatic layout tool, or guide a circuit extractor.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"201 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1989.123245","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The authors describe a system which is able automatically to bring to the attention of the designer significant performance sensitivities which are introduced through interconnection parasitics. The input to the tool is a SPICE file and a performance specification provided by a designer. The output is again a SPICE file, but augmented with those interconnection parasitics which are most significant for the performance specification prescribed by the designer. The value attached to a parasitic is a quantitative estimate of how significant the parasitic is. This information is derived from a simulation of the circuit prior to layout. The list of most significant routing parasitics could be used to provide feedback to a human designer, direct an automatic layout tool, or guide a circuit extractor.<>