A 1.5dB NF, 5.8GHz CMOS low-noise amplifier with on-chip matching

2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI:10.1109/ASSCC.2007.4425741

J. Duster, S. S. Taylor, H. Zhan

引用次数: 3

Abstract

In this paper we describe the design of an integrated 5.8 GIU low noise amplifier in 90 nm CMOS technology. The design is a tuned cascode LNA with on-chip matching that has a sufficiently low noise figure and high gain to enable high receiver sensitivity. The measured performance is NF=l.SdB, gain=28 dB, IIP3= -5 dBm and Pd=15m\V; and NfW.SdB, gain=23 dB, HP3=-17 dBm and Pd=8 m\V.

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具有片上匹配的1.5dB NF, 5.8GHz CMOS低噪声放大器

本文介绍了一种基于90 nm CMOS技术的集成5.8 GIU低噪声放大器的设计。该设计是一个具有片上匹配的调谐级联码LNA，具有足够低的噪声系数和高增益，以实现高接收器灵敏度。实测性能为NF= 1。SdB，增益=28 dB, IIP3= -5 dBm, Pd=15m\V;和NfW。增益=23 dB, HP3=-17 dBm, Pd=8 m\V。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2007 IEEE Asian Solid-State Circuits Conference

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