Pub Date : 2008-09-01DOI: 10.1093/ietele/e91-c.9.1419
M. Hariyama, S. Ishihara, M. Kameyama
This paper presents a novel asynchronous architecture of field-programmable gate arrays (FPGAs) to reduce the power consumption. In the dynamic power consumption of the conventional FPGAs, the power consumed by the switch blocks and clock distribution is dominant since FPGAs have complex switch blocks and the large number of registers for high programmability. To reduce the power consumption of switch blocks and clock distribution, asynchronous bit-serial architecture is proposed. To ensure the correct operation independent of data-path lengths, we use the level-encoded dual-rail encoding and propose its area-efficient implementation. The proposed field-programmable VLSI is implemented in a 90 nm CMOS technology. The delay and the power consumption of the proposed FPVLSI are respectively 61% and 58% of those of 4-phase dual-rail encoding which is the most common encoding in delay sensitive encoding.
{"title":"A Field-programmable VLSI based on an asynchronous bit-serial architecture","authors":"M. Hariyama, S. Ishihara, M. Kameyama","doi":"10.1093/ietele/e91-c.9.1419","DOIUrl":"https://doi.org/10.1093/ietele/e91-c.9.1419","url":null,"abstract":"This paper presents a novel asynchronous architecture of field-programmable gate arrays (FPGAs) to reduce the power consumption. In the dynamic power consumption of the conventional FPGAs, the power consumed by the switch blocks and clock distribution is dominant since FPGAs have complex switch blocks and the large number of registers for high programmability. To reduce the power consumption of switch blocks and clock distribution, asynchronous bit-serial architecture is proposed. To ensure the correct operation independent of data-path lengths, we use the level-encoded dual-rail encoding and propose its area-efficient implementation. The proposed field-programmable VLSI is implemented in a 90 nm CMOS technology. The delay and the power consumption of the proposed FPVLSI are respectively 61% and 58% of those of 4-phase dual-rail encoding which is the most common encoding in delay sensitive encoding.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132437906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-12-01DOI: 10.1109/ASSCC.2007.4425711
H. Amano, Y. Hasegawa, S. Tsutsumi, T. Nakamura, T. Nishimura, V. Tanbunheng, A. Parimala, T. Sano, M. Kato
Coarse grained dynamically reconfigurable processor arrays (DRPAs) have been received an attention as a flexible and efficient off-loading engine in system-on-chips (SoCs). Evaluation results in recent researches revealed that the parameters of optimal processor array structure: granularity, functions, array size, context size and interconnection flexibility, are completely different for each application. That is, DRPAs should be configurable for target SoCs and applications. MuCCRA is a project for developing a DRPA generator which can generate RTL model, testing environment and programming environment for various types of DRPAs just by selecting the specific parameters. Here, two prototype chips MuCCRA-1 and MuCCRA-2 developed in the project are introduced and evaluated. MuCCRA-1 was implemented with Rohm's 0.18 mum CMOS process mainly for multi-media applications, while MuCCRA-2 with ASPLA's 90 nm CMOS process was designed focusing on area optimization used as a cost-effective IP in multi-core SoCs.
{"title":"MuCCRA chips: Configurable dynamically-reconfigurable processors","authors":"H. Amano, Y. Hasegawa, S. Tsutsumi, T. Nakamura, T. Nishimura, V. Tanbunheng, A. Parimala, T. Sano, M. Kato","doi":"10.1109/ASSCC.2007.4425711","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425711","url":null,"abstract":"Coarse grained dynamically reconfigurable processor arrays (DRPAs) have been received an attention as a flexible and efficient off-loading engine in system-on-chips (SoCs). Evaluation results in recent researches revealed that the parameters of optimal processor array structure: granularity, functions, array size, context size and interconnection flexibility, are completely different for each application. That is, DRPAs should be configurable for target SoCs and applications. MuCCRA is a project for developing a DRPA generator which can generate RTL model, testing environment and programming environment for various types of DRPAs just by selecting the specific parameters. Here, two prototype chips MuCCRA-1 and MuCCRA-2 developed in the project are introduced and evaluated. MuCCRA-1 was implemented with Rohm's 0.18 mum CMOS process mainly for multi-media applications, while MuCCRA-2 with ASPLA's 90 nm CMOS process was designed focusing on area optimization used as a cost-effective IP in multi-core SoCs.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122813906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-12-01DOI: 10.1109/ASSCC.2007.4425749
K. Niitsu, Y. Sugimori, Y. Kohama, K. Osada, N. Irie, H. Ishikuro, T. Kuroda
This paper discusses interference of an inductive-coupling link in 65nm CMOS. Electromagnetic interference from power/signal lines and to SRAM was simulated and measured. Interference from power lines for mobile applications (line and space) is smaller than that for high-performance applications (mesh type). Interference from signal lines requires only 9% of additional transmit power even in the worst case of logic circuits. In typical operation range, interference to SRAM is ignorable. Only when supply voltage is much lower than typical range, the bit-line noise from the inductive-coupling link influences SRAM operation. Interference to SRAM is small compared with other influences such as device variations and soft errors.
{"title":"Interference from power/signal lines and to SRAM circuits in 65nm CMOS inductive-coupling link","authors":"K. Niitsu, Y. Sugimori, Y. Kohama, K. Osada, N. Irie, H. Ishikuro, T. Kuroda","doi":"10.1109/ASSCC.2007.4425749","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425749","url":null,"abstract":"This paper discusses interference of an inductive-coupling link in 65nm CMOS. Electromagnetic interference from power/signal lines and to SRAM was simulated and measured. Interference from power lines for mobile applications (line and space) is smaller than that for high-performance applications (mesh type). Interference from signal lines requires only 9% of additional transmit power even in the worst case of logic circuits. In typical operation range, interference to SRAM is ignorable. Only when supply voltage is much lower than typical range, the bit-line noise from the inductive-coupling link influences SRAM operation. Interference to SRAM is small compared with other influences such as device variations and soft errors.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126465567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-12-01DOI: 10.1109/ASSCC.2007.4425781
M. Sasaki, T. Inoue, M. Ikeda, K. Asada
This paper presents a 16times16 temperature probe array using 90 nm IV CMOS, which shows plusmn1.4degC error for 40 ~ 110degC temperature range and achieves a temperature distribution measurement at 40 frames/sec. This array is designed and developed for an operating frequency and supply voltage feedback system corresponding to temperature of each block on a VLSI chip. The continuous thermal monitoring is performed by using accurate four-transistor temperature probe circuits with an error amplifier and two PMOS current sources.
本文提出了一种采用90 nm IV CMOS的16 × 16温度探头阵列，该阵列在40 ~ 110℃温度范围内误差为±1.4℃，实现了40帧/秒的温度分布测量。该阵列是针对VLSI芯片上各模块温度对应的工作频率和电源电压反馈系统而设计和开发的。采用精确的四晶体管温度探头电路，加上误差放大器和两个PMOS电流源，实现了连续热监测。
{"title":"40 frames/sec 16×16 temperature probe array using 90nm 1V CMOS for on-line thermal monitoring on VLSI chip","authors":"M. Sasaki, T. Inoue, M. Ikeda, K. Asada","doi":"10.1109/ASSCC.2007.4425781","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425781","url":null,"abstract":"This paper presents a 16times16 temperature probe array using 90 nm IV CMOS, which shows plusmn1.4degC error for 40 ~ 110degC temperature range and achieves a temperature distribution measurement at 40 frames/sec. This array is designed and developed for an operating frequency and supply voltage feedback system corresponding to temperature of each block on a VLSI chip. The continuous thermal monitoring is performed by using accurate four-transistor temperature probe circuits with an error amplifier and two PMOS current sources.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128278492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425731
Shenghua Zhou, N. Wu
A novel ultra low power temperature sensor for UHF RFID tag chip is presented. The sensor consists of a constant pulse generator, a temperature related oscillator, a counter and a bias. Conversion of temperature to digital output is fulfilled by counting the number of the clocks of the temperature related oscillator in a constant pulse period. The sensor uses time domain comparing, where high power consumption bandgap voltage references and traditional ADCs arc not needed. The sensor is realized in a standard 0.18 mum CMOS process, and the area is only 0.2 mm2. The accuracy of the temperature sensor is plusmn1degC after calibration. The power consumption of the sensor is only 0.9 muW.
提出了一种用于超高频RFID标签芯片的超低功耗温度传感器。该传感器由恒定脉冲发生器、温度相关振荡器、计数器和偏置组成。温度到数字输出的转换是通过在恒定的脉冲周期内计算温度相关振荡器的时钟数来实现的。该传感器采用时域比较，不需要高功耗带隙电压参考和传统的adc。该传感器采用标准的0.18 μ m CMOS工艺实现，面积仅为0.2 mm2。温度传感器校准后的精度为±1℃。传感器的功耗仅为0.9 muW。
{"title":"A novel ultra low power temperature sensor for UHF RFID tag chip","authors":"Shenghua Zhou, N. Wu","doi":"10.1109/ASSCC.2007.4425731","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425731","url":null,"abstract":"A novel ultra low power temperature sensor for UHF RFID tag chip is presented. The sensor consists of a constant pulse generator, a temperature related oscillator, a counter and a bias. Conversion of temperature to digital output is fulfilled by counting the number of the clocks of the temperature related oscillator in a constant pulse period. The sensor uses time domain comparing, where high power consumption bandgap voltage references and traditional ADCs arc not needed. The sensor is realized in a standard 0.18 mum CMOS process, and the area is only 0.2 mm2. The accuracy of the temperature sensor is plusmn1degC after calibration. The power consumption of the sensor is only 0.9 muW.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116713990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425704
Y. Ikeda, M. Frey, A. Matsuzawa
A 14-bit digitally calibrated digital-to-analog converter (DAC) is presented. This DAC uses a simple current comparator for the current measurement during calibration instead of a high-resolution ADC. Therefore, compared to a calibration scheme utilizing a high-resolution ADC, a faster calibration cycle is possible with smaller additional circuits. To reduce the additional area for calibration and error compensation, the lowest 8-bit DAC is used for both error correction and for normal operation; the additional DACs required for calibration are only of 3-bit and of 7-bit resolution. Nevertheless, a large calibration range is attained. Full 14-bit resolution is achieved on a small chip-area (0.72 mm2). The measurement results show that the spurious free dynamic range is 83.4 (46.6) dBc for signals of 6 kHz (30 MHz) at an update rate of 100 MS/s.
{"title":"A 14-bit 100-MS/s digitally calibrated binary-weighted current-steering CMOS DAC without calibration ADC","authors":"Y. Ikeda, M. Frey, A. Matsuzawa","doi":"10.1109/ASSCC.2007.4425704","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425704","url":null,"abstract":"A 14-bit digitally calibrated digital-to-analog converter (DAC) is presented. This DAC uses a simple current comparator for the current measurement during calibration instead of a high-resolution ADC. Therefore, compared to a calibration scheme utilizing a high-resolution ADC, a faster calibration cycle is possible with smaller additional circuits. To reduce the additional area for calibration and error compensation, the lowest 8-bit DAC is used for both error correction and for normal operation; the additional DACs required for calibration are only of 3-bit and of 7-bit resolution. Nevertheless, a large calibration range is attained. Full 14-bit resolution is achieved on a small chip-area (0.72 mm2). The measurement results show that the spurious free dynamic range is 83.4 (46.6) dBc for signals of 6 kHz (30 MHz) at an update rate of 100 MS/s.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"39 12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129077745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425794
S. Ito
Summary form only given. After having enjoyed the years of staggering growth in the 90's, the semiconductor industry is being matured. Today, it is still a growing industry, at a slower pace, as it continues to expand its reach to cover a growing number of all industries. While miniaturization is still an important consideration for many semiconductor manufacturers, the multitude of complex technology and economical scale limitations are posing as new challenges. Today, there is no single driving force to fuel the growth of the semiconductor industry. Under this new paradigm, it is important re-evaluate the business model of the semiconductor industry, together with two keywords, "convergence" and "divergence." "Convergence" enables utilization of various application contents beyond time and space, allowing consumers to access data from anywhere, anytime. On the other hand, "divergence" accelerates segmentation, bringing solutions such as electronics systems tailored for each individual need and widely distributed networked systems. In the ubiquitous era, these seemingly contradicting elements become the foundation for establishing a new business model. Given the change, what is required for technology is also changing. What the industry really needs is a system-centric innovation approach centered on software, to enable delivery of a wide spectrum of applications, rather than a conventional hardware-centric approach. This paper discussed how to enable such innovations as well as how to overcome other future challenges in the industry.
{"title":"Convergence and divergence in parallel for the ubiquitous era","authors":"S. Ito","doi":"10.1109/ASSCC.2007.4425794","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425794","url":null,"abstract":"Summary form only given. After having enjoyed the years of staggering growth in the 90's, the semiconductor industry is being matured. Today, it is still a growing industry, at a slower pace, as it continues to expand its reach to cover a growing number of all industries. While miniaturization is still an important consideration for many semiconductor manufacturers, the multitude of complex technology and economical scale limitations are posing as new challenges. Today, there is no single driving force to fuel the growth of the semiconductor industry. Under this new paradigm, it is important re-evaluate the business model of the semiconductor industry, together with two keywords, \"convergence\" and \"divergence.\" \"Convergence\" enables utilization of various application contents beyond time and space, allowing consumers to access data from anywhere, anytime. On the other hand, \"divergence\" accelerates segmentation, bringing solutions such as electronics systems tailored for each individual need and widely distributed networked systems. In the ubiquitous era, these seemingly contradicting elements become the foundation for establishing a new business model. Given the change, what is required for technology is also changing. What the industry really needs is a system-centric innovation approach centered on software, to enable delivery of a wide spectrum of applications, rather than a conventional hardware-centric approach. This paper discussed how to enable such innovations as well as how to overcome other future challenges in the industry.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131948028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425729
W. Chiu, Tai-Shun Chan, Tsung-Hsien Lin
This work presents a phase-locked loop (PLL) with a fast-locking capability. The PLL incorporates a proposed digital discriminator aided phase detector (DAPD) to expedite the loop settling. The DAPD enables a fast locking by sensing the input phase error to adjust the programmable charge pump and loop filter. Moreover, two digital frequency dividers, one divide-by-2 and one divide-by-4/5, are proposed to accomplish low-power and high-speed divider operation. The PLL is fabricated in a 0.18-mum CMOS process. With the proposed digital DAPD, the settling time is considerably reduced to 20 mus without sacrificing the characteristics of a 40-kHz loop bandwidth at lock. The measured 5.5-GHz PLL phase noise at 1-MHz offset is -110.8 dBc/Hz, and the reference spurs at 10-MHz. offset are lower than -75 dBc. The whole PLL consumes 9 mA from a 1.8-V supply voltage, while the two high-frequency dividers consume 1.4 mA only.
{"title":"A 5.5-GHz 16-mW fast-locking frequency synthesizer in 0.18-μm CMOS","authors":"W. Chiu, Tai-Shun Chan, Tsung-Hsien Lin","doi":"10.1109/ASSCC.2007.4425729","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425729","url":null,"abstract":"This work presents a phase-locked loop (PLL) with a fast-locking capability. The PLL incorporates a proposed digital discriminator aided phase detector (DAPD) to expedite the loop settling. The DAPD enables a fast locking by sensing the input phase error to adjust the programmable charge pump and loop filter. Moreover, two digital frequency dividers, one divide-by-2 and one divide-by-4/5, are proposed to accomplish low-power and high-speed divider operation. The PLL is fabricated in a 0.18-mum CMOS process. With the proposed digital DAPD, the settling time is considerably reduced to 20 mus without sacrificing the characteristics of a 40-kHz loop bandwidth at lock. The measured 5.5-GHz PLL phase noise at 1-MHz offset is -110.8 dBc/Hz, and the reference spurs at 10-MHz. offset are lower than -75 dBc. The whole PLL consumes 9 mA from a 1.8-V supply voltage, while the two high-frequency dividers consume 1.4 mA only.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"120 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133651414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425787
Yanhui Yang, Muhua Han, Sudong Yu, Shaojun Wei
Personal information storage and data processing are two of the key issues in mobile device product development. SSC give a new solution to solve these handicaps on account of that it is different from traditional SD card, MMC card and USB device. It tries to integrate high performance calculation, large volume memory and some popular flash card interfaces together into one chip, which leads to a new generation of smart controller for mobile storage. SSC can be used in mobile phones, digital cameras, and other electronic devices which need not only large memory size but also data processing and information management ability. Mega-Byte Class SIM is a typical usage. It can provide an attractive and profitable value-added-service (VAS) platform to telecom carriers. Assisted by the new SIM, the mobile phone can largely expand and strengthen it's user experience, WEP service is a excellent practice benefit from it's GUI system to provide renewable applications. A programmable chip platform and flexible software system are absolutely necessarily. This paper will focus on these topics and give some key discussions on smart controller chip and major application software design technology. One successfully developed SoC will be presented also in this paper.
{"title":"SSC™ - A new generation of smart controller for mobile storage","authors":"Yanhui Yang, Muhua Han, Sudong Yu, Shaojun Wei","doi":"10.1109/ASSCC.2007.4425787","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425787","url":null,"abstract":"Personal information storage and data processing are two of the key issues in mobile device product development. SSC give a new solution to solve these handicaps on account of that it is different from traditional SD card, MMC card and USB device. It tries to integrate high performance calculation, large volume memory and some popular flash card interfaces together into one chip, which leads to a new generation of smart controller for mobile storage. SSC can be used in mobile phones, digital cameras, and other electronic devices which need not only large memory size but also data processing and information management ability. Mega-Byte Class SIM is a typical usage. It can provide an attractive and profitable value-added-service (VAS) platform to telecom carriers. Assisted by the new SIM, the mobile phone can largely expand and strengthen it's user experience, WEP service is a excellent practice benefit from it's GUI system to provide renewable applications. A programmable chip platform and flexible software system are absolutely necessarily. This paper will focus on these topics and give some key discussions on smart controller chip and major application software design technology. One successfully developed SoC will be presented also in this paper.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133662832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425793
J. Hu
This paper discusses the outsourcing and collaboration strategy that semiconductor companies have adopted in order to maintain the pace of Moore's law. Major IDM companies have led this trend, with many announcing fab-lite/asset-lite models that include outsourcing to foundries. Also discussed is the overall collaboration that has taken place throughout the entire supply chain between IDMs, foundries, design companies, and EDA vendors, and the necessary acceleration of this trend as semiconductor process and manufacturing technologies continue to gain in complexity.
{"title":"Recent business model and technology trends and their impact on the semiconductor industry","authors":"J. Hu","doi":"10.1109/ASSCC.2007.4425793","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425793","url":null,"abstract":"This paper discusses the outsourcing and collaboration strategy that semiconductor companies have adopted in order to maintain the pace of Moore's law. Major IDM companies have led this trend, with many announcing fab-lite/asset-lite models that include outsourcing to foundries. Also discussed is the overall collaboration that has taken place throughout the entire supply chain between IDMs, foundries, design companies, and EDA vendors, and the necessary acceleration of this trend as semiconductor process and manufacturing technologies continue to gain in complexity.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131662508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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