VLSI chip-set for personal computers

Abstract

This paper will describe a V U 1 chip-set for Personal Computers. It consists of Peripheral Controller (PERIJ made of I1 standard peripheral mega-macro block, Text Controller (CRZT), and Graphics Controller (CRTG). The chips fully utilize hierarchical automatic layout design system. 205K transistors have been integrated by a three chip-set. They have been fabricated by I.5pm double metal-layer CMOS process technology. The chip-set allows to design a personal computer of M-size with CPU, memory and some inteqace logics. The personal computer consumes only 114 of power. compared to a standard version with the same system configuration. Introduction : This paper describes a VLSI chip-set for Personal Computers. The set consists of Peripheral Controller (PERI), Text Controller (CRm), and Graphics Controller bus and address bus. Bus controller gives bus interface Control signals, such as memory readlwrite and I10 readwrite, to mega-macro blocks. Custom-macro blocks are provided to realize user-defined functions, such as timing control of the device, extemal interface, offchip memory interface, and so on. Standard cell approach realizes these custom-macros. Microphotograph of the chip is shown in Fig.3. The CRTT contains a Graphic Display Controller (GDC) mega-macro and 5.4K-gate custom-macro.The CRTG contains a GDC and 11 .5K-gate custom-macro. Table 1 summarizes features of three chips. Fig.4 shows an example of PC system configuration by the chip-set. As is shown, only the interface logics are required, in addition to ROM/RAM and CPU. Mega-Macro Blocks : The mega-macro blocks are the (CKIti). A VLSI chip-set which integrates various standard peripheral LSIs is highly required by system vendors so that a small system with low Power consumption can be realized. In this case, the chip-set should be software-compatible with the off-the-shelf standard peripheral LSIs, and should be developedin shortperiod. A simple way of implementing such VLSIs without modifying the original LSIS tends to have enormous chip area. Entirely new design of standard LSI by another technology, such as standard cell approach, also has enormous man-power to modify existing standard LSI circuit for standard cell. mozified versions of standard m&roprocessor peripheral controllers. Features of mega-macros are shown in Table 2. Use of a mega-macro block reduces the number of transistors and area size, compared to the standard cell approach. For example, the PI0 mega-macro block has 2,500 transistors, however it would have 4,400 transistors if it were designed by using standard cell technique. In the PERI-chip case, this technique has reduced 37% of total chip size than the standard cell design. The original layout of standard LSIs were used as first approximation of mega-macro blocks, then VO pads were stripped out to have the smallest block area. It has brought 25% to 54% of area reduction, compared to ones with The chip-set has been developed to fulfill these I/O Dads. The oumut drivers of each mega-macro block has requirements by utilizing following techniques: * Peripheral megamacro block made of standard LSI * Hierarchical automatic design system * Double metal-layer 1.5pn CMOS process technology Use of standard LSI as the base of mega-macro block as well as automatic layout system has reduced man-vower. comoared beeiredesigned tobe able to drive the intehal common-bus. Process Conversion : BC and DMAC in the PERI chip have been redesigned for mega-macro implementation in order to unify the process technology. The double metal-layer Drocess technoloev. which can be easilv transferred from the IO manual implkmentstion. Double metal-lay& technology also realized reasonable chip size, although original LSIs were briginal single &&-layer pmcess. was ;mployed to utiliic the original lsyout design. realized by single metal-layer technolog< The process technology also enables high design flexibility of automatic layout design, maintaining original LSIs performance. The chip-set has been fabricated by 1.5pm double metal layer CMOS technology and approximately 205K transistors have been integrated in the chip-set. It has eight peripherals functions, and has realized 114 of power consumption than the standard LSI based system. Chip-Set Structure : Chip-set structure is shown in Fig.1. Each chip contains two different types of blocks: mega-macro blocks and custom-macro blocks. The P E N chip has eleven mega-macro blocks in seven types. They are: Floppy Disk Controller (FDC), 8-level pn’ority Intempt Controller (PIC), 4-channel 8-biUldbit DMA Controller (DMAC), 3-channel 16-bit Timer (TIM), Bus Controller (BC), SynchronousIAsynchronous Serial 110 Controller (SIO). and triple byte-wise Parallel YO Controller (PIO). In addition, it has 5K-gate custom-macro to implement other functions. Block diagram is shown in Fig.2. In the chip, mega-macro blocks are interconnected through the intemal data . Automatic Design : The chip-set was designed by using hierarchical automatic layout system. Three automatic layout programs were employed in this system. Poly-Cell Layout Program designs custom-macro blocks. Hierarchical layout design of the chip requires layout programs to place and interconnect various macro blocks in different sizes and shapes. Floor Planner and Building Block Layout Program has been applied to placements and interconnections of macro blocks,respectively. Fig. 5 shows this layout system and design flow. First, the Floor Planner does macro block placements prior to the actual design of each custom-macro block. It tries to place macro blocks in smallest area by determining the size, aspect ratio, and terminal positions of each custom-macro block. Once the floor plan is decided, custom-macro blocks are laid out according to the result of floor plan. Then, custom-macro blocks, mega-macro blocks, and VO blocks are interconnected by the Building Block Layout Program. This process is iterated in short TAT (turn-around time), until optimal layout is achieved.This automatic approach has brought