VLSI design for de-blocking filter of H.264 decoder

Abstract

De-blocking filter as the output of H.264 decoder affects the speed and throughput of the decoder directly. Based on the fact that the de-blocking filter applied in main profile is demanded more in speed and throughput than in area and consumption, this paper put forward a new structure for de-blocking filter system as well as the most timing cost edge filtering according to the filter algorithm. This circuit is implemented with Xilinx Vertex4 XC4VSX35, and the simulation result indicates this structure is more efficient in area and speed to some degree.