A 24-mW 0.02-mm2 1.5-GHz DLL-Based Frequency Multiplier in 130-nm CMOS

Abstract

This paper presents a low-power small-area DLL-based frequency multiplier. Instead of using edge combiner-based clock synthesis scheme, the proposed frequency multiplier utilizes a ring oscillator, which is controlled by a DLL. An injection-locked slave ring oscillator is used for jitter suppression. The implementation of the proposed structure in 130-nm CMOS occupies an area of 0.02 mm2. It operates in the frequency range of 100 MHz to 1.5 GHz while consuming 24-mW power from a 1.2-V supply at 1.5 GHz. The measured output phase noise at 1.5 GHz is -100.1 dBc/Hz at a 4-MHz frequency offset.