Tolerant design of low power D Flip Flop using GDI and DSTC for higher performance

Abstract

This article clarifies another execution of productive D-Flip-Flop (DFF) utilizing Gate-Diffusion-Input (GDI) strategy and DSTC. This DFF outline permits diminishing force delay item and territory of the circuit, while keeping up low many-sided quality of rationale configuration. Execution correlation with other DFF plan systems is exhibited, regarding entryway range, number of gadgets, postpone and power scattering, indicating points of interest and disadvantages of GDI DFF when contrasted with ordinary strategy. The execution is completed by HSPICE reenactment with 180 nm & 90 nm CMOS innovation.