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2015 International Conference on Communication Networks (ICCN)最新文献

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Design of novel low power dynamic latch comparator using multi-Fin technology 基于多翅片技术的新型低功耗动态锁存比较器设计
Pub Date : 2015-11-01 DOI: 10.1109/ICCN.2015.22
Akanksha Singh, Aushi Marwah, S. Akashe
The designing of high speed (ADC) analog to digital converter in low power for improving the performance like speed and power efficiency in dynamic latch comparator. This paper deals in reduction of leakage power and propagation delay of this dynamic latch comparator. Using various techniques designers can simulate and observe the different factors for enhancing the performance of the circuit. The conventional circuit is modified by using FinFET technique and with the help of proposed circuit the performance of the comparator circuit is enhanced. Performance parameters of the comparator like average power dissipation, energy efficiency, delay are being improved by using FinFET technique as compared to that of the conventional comparator circuit. Leakage power obtained using FinFET is 56.84 pW which is very less than that of conventional comparator. Simulation is done in 45-nm CMOS technology which confirms the analysis results.
为提高动态锁存比较器的速度和功率效率等性能,设计了低功耗高速模数转换器。本文研究了该动态锁存比较器的泄漏功率和传输延迟的降低。设计人员可以使用各种技术来模拟和观察提高电路性能的不同因素。采用FinFET技术对传统电路进行了改进,提高了比较电路的性能。与传统的比较器电路相比,采用FinFET技术可以提高比较器的平均功耗、能量效率、延迟等性能参数。使用FinFET获得的漏功率为56.84 pW,比传统比较器的漏功率小得多。在45纳米CMOS技术下进行了仿真,验证了分析结果。
{"title":"Design of novel low power dynamic latch comparator using multi-Fin technology","authors":"Akanksha Singh, Aushi Marwah, S. Akashe","doi":"10.1109/ICCN.2015.22","DOIUrl":"https://doi.org/10.1109/ICCN.2015.22","url":null,"abstract":"The designing of high speed (ADC) analog to digital converter in low power for improving the performance like speed and power efficiency in dynamic latch comparator. This paper deals in reduction of leakage power and propagation delay of this dynamic latch comparator. Using various techniques designers can simulate and observe the different factors for enhancing the performance of the circuit. The conventional circuit is modified by using FinFET technique and with the help of proposed circuit the performance of the comparator circuit is enhanced. Performance parameters of the comparator like average power dissipation, energy efficiency, delay are being improved by using FinFET technique as compared to that of the conventional comparator circuit. Leakage power obtained using FinFET is 56.84 pW which is very less than that of conventional comparator. Simulation is done in 45-nm CMOS technology which confirms the analysis results.","PeriodicalId":431743,"journal":{"name":"2015 International Conference on Communication Networks (ICCN)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124907028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design and analysis of switch mode power supply using CMOS single-phase full bridge rectifier 基于CMOS单相全桥整流器的开关电源设计与分析
Pub Date : 2015-11-01 DOI: 10.1109/ICCN.2015.72
Shubham Kumar, Prateek Jain, S. Akashe
This paper presents the design of a low leakage CMOS based switch mode power supply. The switch mode power supply converts the available deregulated A.C or D.C input supply to a regulated D.C output supply. This paper reviews the limitations of conventional linear regulated power supply and focuses on the advantages of switch mode power supply (SMPS) technique. The high frequency transformer used in the proposed circuit is much smaller in a size and weight compared to the low pitch transformer of the linear power supply circuit. The switching losses in modern switches like MOS are much lowered as compared to the loss in the linear element. The proposed circuit easily filtered the high frequency ripple produced in the circuit using smaller volumes of filtering elements. Leakage current, leakage power dissipation, average power dissipation and delay performance parameters are calculated. Due to simulation results, it is realized that the leakage current and power dissipation are reduced and delay is improved (reduced delay).The complete simulation and calculation method have been done in 45 nm technology at cadence virtuoso tool. The circuits were operated at 0.7v power supply.
本文设计了一种基于CMOS的低漏电流开关电源。开关模式电源将可用的去调节的交流或直流输入电源转换为调节的直流输出电源。本文综述了传统线性稳压电源的局限性,重点介绍了开关电源技术的优点。与线性电源电路的低间距变压器相比,所提出电路中使用的高频变压器在尺寸和重量上要小得多。与线性元件的损耗相比,MOS等现代开关的开关损耗要低得多。该电路使用更小体积的滤波元件,可以很容易地滤波电路中产生的高频纹波。计算泄漏电流、泄漏功耗、平均功耗和延迟性能参数。通过仿真结果,实现了减少漏电流和功耗,提高延时(reduced delay)。在cadence virtuoso工具上以45nm工艺完成了完整的仿真计算方法。电路在0.7v电源下工作。
{"title":"Design and analysis of switch mode power supply using CMOS single-phase full bridge rectifier","authors":"Shubham Kumar, Prateek Jain, S. Akashe","doi":"10.1109/ICCN.2015.72","DOIUrl":"https://doi.org/10.1109/ICCN.2015.72","url":null,"abstract":"This paper presents the design of a low leakage CMOS based switch mode power supply. The switch mode power supply converts the available deregulated A.C or D.C input supply to a regulated D.C output supply. This paper reviews the limitations of conventional linear regulated power supply and focuses on the advantages of switch mode power supply (SMPS) technique. The high frequency transformer used in the proposed circuit is much smaller in a size and weight compared to the low pitch transformer of the linear power supply circuit. The switching losses in modern switches like MOS are much lowered as compared to the loss in the linear element. The proposed circuit easily filtered the high frequency ripple produced in the circuit using smaller volumes of filtering elements. Leakage current, leakage power dissipation, average power dissipation and delay performance parameters are calculated. Due to simulation results, it is realized that the leakage current and power dissipation are reduced and delay is improved (reduced delay).The complete simulation and calculation method have been done in 45 nm technology at cadence virtuoso tool. The circuits were operated at 0.7v power supply.","PeriodicalId":431743,"journal":{"name":"2015 International Conference on Communication Networks (ICCN)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123431406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Comparative analysis of AODV and DSR scalability in MANET MANET中AODV和DSR可扩展性的比较分析
Pub Date : 2015-11-01 DOI: 10.1109/ICCN.2015.15
C. Mafirabadza, P. Khatri, Reena Chauhan
MANET is an Ad-hoc mobile network which consists of autonomous mobile nodes which are self organizing in an infrastructure less setup. This means that there is no centralized system, hence the mobile nodes have to perform routing and aggregations and forward the information to other mobile nodes. Routing is a major challenge in Mobile ad-hoc networks due to the mobility of nodes. In this paper a simulation analysis of two common routing protocols: Ad-hoc on demand distance vector (AODV) and Dynamic source routing (DSR) is performed varying the node density in a fixed size area with highly mobile nodes moving at random speeds. Simulation is performed using the Network Simulator 2 (NS2).
MANET是一种由自主移动节点组成的自组织移动网络。这意味着没有集中的系统,因此移动节点必须执行路由和聚合,并将信息转发给其他移动节点。由于节点的移动性,路由是移动自组织网络中的一个主要挑战。本文对两种常见的路由协议:Ad-hoc随需应变距离矢量(AODV)和动态源路由(DSR)进行了仿真分析,在固定大小的区域内改变节点密度,高移动节点以随机速度移动。使用网络模拟器2 (NS2)进行仿真。
{"title":"Comparative analysis of AODV and DSR scalability in MANET","authors":"C. Mafirabadza, P. Khatri, Reena Chauhan","doi":"10.1109/ICCN.2015.15","DOIUrl":"https://doi.org/10.1109/ICCN.2015.15","url":null,"abstract":"MANET is an Ad-hoc mobile network which consists of autonomous mobile nodes which are self organizing in an infrastructure less setup. This means that there is no centralized system, hence the mobile nodes have to perform routing and aggregations and forward the information to other mobile nodes. Routing is a major challenge in Mobile ad-hoc networks due to the mobility of nodes. In this paper a simulation analysis of two common routing protocols: Ad-hoc on demand distance vector (AODV) and Dynamic source routing (DSR) is performed varying the node density in a fixed size area with highly mobile nodes moving at random speeds. Simulation is performed using the Network Simulator 2 (NS2).","PeriodicalId":431743,"journal":{"name":"2015 International Conference on Communication Networks (ICCN)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122455237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
The new multifin approach for mitigation of leakage in an Operational Transconductance Amplifier 运算跨导放大器中减少漏损的新多翅片方法
Pub Date : 2015-11-01 DOI: 10.1109/ICCN.2015.63
Prateek Tiwari, R. S. Tomar, S. Akashe
In this paper presents the design and analysis of Conventional Operational Transconductance Amplifier for use in novel FinFET based OTA. OTA is an analog circuit and it has differential input voltage controlled current source (VCCS). OTA is a basic building block in analog circuit. In this, paper we focus on different-different supply voltage to find such type parameter like leakage power, integrated noise, leakage current, power consumption. The proposed design using FinFET has enhanced the performance parameter of the conventional OTA design. By using, novel FinFET OTA we reduce power consumption 1.024mW.The proposed OTA (implemented with FINFET) had fixed bias voltage at 0.7μA and supply voltage is 0.7V. The design and simulation of FINFET based OTA is done by using 45nm technology at cadence virtuoso version 6.1 platforms.
本文介绍了用于新型FinFET OTA的传统运算跨导放大器的设计和分析。OTA是一种模拟电路,它具有差分输入电压控制电流源(VCCS)。OTA是模拟电路的基本组成部分。本文以不同的电源电压为研究对象,找出泄漏功率、综合噪声、泄漏电流、功耗等类型参数。采用FinFET的设计提高了传统OTA设计的性能参数。通过使用新颖的FinFET OTA,我们减少了1.024mW的功耗。采用FINFET实现的OTA具有0.7μA的固定偏置电压和0.7V的电源电压。基于FINFET的OTA的设计和仿真是在cadence virtuoso version 6.1平台上使用45nm技术完成的。
{"title":"The new multifin approach for mitigation of leakage in an Operational Transconductance Amplifier","authors":"Prateek Tiwari, R. S. Tomar, S. Akashe","doi":"10.1109/ICCN.2015.63","DOIUrl":"https://doi.org/10.1109/ICCN.2015.63","url":null,"abstract":"In this paper presents the design and analysis of Conventional Operational Transconductance Amplifier for use in novel FinFET based OTA. OTA is an analog circuit and it has differential input voltage controlled current source (VCCS). OTA is a basic building block in analog circuit. In this, paper we focus on different-different supply voltage to find such type parameter like leakage power, integrated noise, leakage current, power consumption. The proposed design using FinFET has enhanced the performance parameter of the conventional OTA design. By using, novel FinFET OTA we reduce power consumption 1.024mW.The proposed OTA (implemented with FINFET) had fixed bias voltage at 0.7μA and supply voltage is 0.7V. The design and simulation of FINFET based OTA is done by using 45nm technology at cadence virtuoso version 6.1 platforms.","PeriodicalId":431743,"journal":{"name":"2015 International Conference on Communication Networks (ICCN)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129296758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and optimization of narrow band low noise amplifier using 0.18µm CMOS 0.18µm CMOS窄带低噪声放大器的设计与优化
Pub Date : 2015-11-01 DOI: 10.1109/ICCN.2015.21
Hasmukh P. Koringa, V. Shah
In this paper, an optimized design procedure based on evolutionary algorithms for automatic synthesis of a current reuse cascode fully integrated low noise amplifiers (LNA) targeted @2.4GHz is discussed. Here genetic Algorithm is intended to compute the circuit elements values and bias levels capable of maintaining the best level of gain, input matching, and power consumption. The circuit simulate using 0.18μm RF CMOS TSMC technology for to evaluate performance. Automatic circuit design using evolutionary optimization algorithm optimized design taking less computation time compare to tremendous manual trial. The Simulation results show the power gain (S21) and input matching (S11) are 26dB and -13dB respectively @2.4GHz. Simulation results demonstrate output reflection (S12) is less than -35dB and current sink form 1.8V supply is only 5.6mA.
本文讨论了一种基于进化算法的电流复用级联码全集成低噪声放大器(LNA)自动合成优化设计过程。这里遗传算法的目的是计算电路元件的值和偏置水平能够维持最佳水平的增益,输入匹配,和功耗。电路采用0.18μm RF CMOS TSMC技术进行仿真,以评估其性能。采用进化优化算法的自动电路设计与大量的人工试验相比,优化设计所需的计算时间更少。仿真结果表明,在2.4 ghz时,功率增益(S21)和输入匹配(S11)分别为26dB和-13dB。仿真结果表明,输出反射(S12)小于-35dB, 1.8V电源的电流吸收仅为5.6mA。
{"title":"Design and optimization of narrow band low noise amplifier using 0.18µm CMOS","authors":"Hasmukh P. Koringa, V. Shah","doi":"10.1109/ICCN.2015.21","DOIUrl":"https://doi.org/10.1109/ICCN.2015.21","url":null,"abstract":"In this paper, an optimized design procedure based on evolutionary algorithms for automatic synthesis of a current reuse cascode fully integrated low noise amplifiers (LNA) targeted @2.4GHz is discussed. Here genetic Algorithm is intended to compute the circuit elements values and bias levels capable of maintaining the best level of gain, input matching, and power consumption. The circuit simulate using 0.18μm RF CMOS TSMC technology for to evaluate performance. Automatic circuit design using evolutionary optimization algorithm optimized design taking less computation time compare to tremendous manual trial. The Simulation results show the power gain (S21) and input matching (S11) are 26dB and -13dB respectively @2.4GHz. Simulation results demonstrate output reflection (S12) is less than -35dB and current sink form 1.8V supply is only 5.6mA.","PeriodicalId":431743,"journal":{"name":"2015 International Conference on Communication Networks (ICCN)","volume":" 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132123376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Convolution coding and applications: A performance analysis under AWGN channel 卷积编码及其应用:AWGN信道下的性能分析
Pub Date : 2015-11-01 DOI: 10.1109/ICCN.2015.17
Rinu Ann Baby
The convolutional coding technique is used to encode and decode a continuous stream of bits. The basic concept behind the convolution is the overlapping of two signals to form the other one. Because of the nature of convolution coding technique the binary bit stream source is convolved by applying some binary operations on them. It is a memory based system, which means the output bit is dependent of the current bit being encoded as well as the previous bit stream stored in the memory. This paper proposes the model demonstrating convolutional coding technique with varying AWGN parameters with the implementation aid of MATLAB Simulink and also the encoding and decoding technique used in the application DVB-T (Digital Video Broadcasting-Terrestrial). The Simulink model with Convolution encoder and Viterbi Decoder in the punctured system provides encoding and decoding of high data rate. The puncturing technique uses standard rate one by two encoders and decoders. The main applications of convolution coding is in the deep space applications and in wireless communication systems.
卷积编码技术用于对连续的比特流进行编码和解码。卷积背后的基本概念是两个信号重叠形成另一个信号。由于卷积编码技术的特性,通过对二进制码流源进行一些二进制运算,将二进制码流源进行卷积。它是一个基于内存的系统,这意味着输出位依赖于当前被编码的位以及存储在内存中的前位流。本文提出了用MATLAB Simulink实现不同AWGN参数下的卷积编码技术的模型,以及应用于DVB-T(地面数字视频广播)的编解码技术。在穿孔系统中使用卷积编码器和维特比解码器的Simulink模型提供了高数据速率的编解码。穿刺技术采用标准速率,一个接两个编码器和解码器。卷积编码的主要应用是深空应用和无线通信系统。
{"title":"Convolution coding and applications: A performance analysis under AWGN channel","authors":"Rinu Ann Baby","doi":"10.1109/ICCN.2015.17","DOIUrl":"https://doi.org/10.1109/ICCN.2015.17","url":null,"abstract":"The convolutional coding technique is used to encode and decode a continuous stream of bits. The basic concept behind the convolution is the overlapping of two signals to form the other one. Because of the nature of convolution coding technique the binary bit stream source is convolved by applying some binary operations on them. It is a memory based system, which means the output bit is dependent of the current bit being encoded as well as the previous bit stream stored in the memory. This paper proposes the model demonstrating convolutional coding technique with varying AWGN parameters with the implementation aid of MATLAB Simulink and also the encoding and decoding technique used in the application DVB-T (Digital Video Broadcasting-Terrestrial). The Simulink model with Convolution encoder and Viterbi Decoder in the punctured system provides encoding and decoding of high data rate. The puncturing technique uses standard rate one by two encoders and decoders. The main applications of convolution coding is in the deep space applications and in wireless communication systems.","PeriodicalId":431743,"journal":{"name":"2015 International Conference on Communication Networks (ICCN)","volume":"9 10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134565252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Performance and analysis of 10T Full Adder using MTCMOS technique 采用MTCMOS技术的10T全加法器性能及分析
Pub Date : 2015-11-01 DOI: 10.1109/ICCN.2015.56
V. Agarawal, Ravindra Shrivastava, S. Akashe
Full Adder performs addition and therefore in microprocessor and digital signal processor, it is used for arithmetic operation, for comparison and for access the address in memory. Improvement of this circuit would impart a greater impact on the performance of large systems where it has been employed. For improvement of power and delay performance in full adder, the 10T structure based static energy recovery type full Adder (SERF) has been utilized with MTCMOS technique at 45nm technology. MTCMOS (Multi-Threshold Complementary Metal Oxide Semiconductor) technique has been emerged as a promising and popular circuit technique for further improvement in performance (i.e. reduction in delay and power minimization) of full adder. The paper here illustrates the analysis of leakage current, active power, delay and noise with power supply of (0.7 V). The reduction in power consumption in the structure represented is computed as 90.27nW and propagation delay of 10.24ns, which significantly improves and makes the circuit more efficient and reliable. The leakage current has been reduced and lies between 1.004-1.771pA with different supply voltages from 0.5v to 0.9v. The adder has been analyzed for various parameters. All simulation results are performed with 45nm CMOS technology, 20ns access time and 0.05GHZ frequency using cadence virtuoso tool.
全加器执行加法,因此在微处理器和数字信号处理器中,它用于算术运算、比较和访问存储器中的地址。该电路的改进将对已采用该电路的大型系统的性能产生更大的影响。为了提高全加法器的功率和延迟性能,将基于10T结构的静态能量回收型全加法器(SERF)与45纳米MTCMOS技术结合使用。MTCMOS(多阈值互补金属氧化物半导体)技术已成为一种有前途和流行的电路技术,以进一步提高全加法器的性能(即减少延迟和最小化功耗)。本文对(0.7 V)电源下的漏电流、有功功率、延迟和噪声进行了分析,计算得出所示结构的功耗降低为90.27nW,传播延迟为10.24ns,显著提高了电路的效率和可靠性。在0.5v ~ 0.9v的不同电源电压下,漏电流减小在1.004 ~ 1.771 pa之间。对加法器的各种参数进行了分析。所有仿真结果均采用45nm CMOS技术,20ns访问时间和0.05GHZ频率,使用cadence virtuoso工具进行。
{"title":"Performance and analysis of 10T Full Adder using MTCMOS technique","authors":"V. Agarawal, Ravindra Shrivastava, S. Akashe","doi":"10.1109/ICCN.2015.56","DOIUrl":"https://doi.org/10.1109/ICCN.2015.56","url":null,"abstract":"Full Adder performs addition and therefore in microprocessor and digital signal processor, it is used for arithmetic operation, for comparison and for access the address in memory. Improvement of this circuit would impart a greater impact on the performance of large systems where it has been employed. For improvement of power and delay performance in full adder, the 10T structure based static energy recovery type full Adder (SERF) has been utilized with MTCMOS technique at 45nm technology. MTCMOS (Multi-Threshold Complementary Metal Oxide Semiconductor) technique has been emerged as a promising and popular circuit technique for further improvement in performance (i.e. reduction in delay and power minimization) of full adder. The paper here illustrates the analysis of leakage current, active power, delay and noise with power supply of (0.7 V). The reduction in power consumption in the structure represented is computed as 90.27nW and propagation delay of 10.24ns, which significantly improves and makes the circuit more efficient and reliable. The leakage current has been reduced and lies between 1.004-1.771pA with different supply voltages from 0.5v to 0.9v. The adder has been analyzed for various parameters. All simulation results are performed with 45nm CMOS technology, 20ns access time and 0.05GHZ frequency using cadence virtuoso tool.","PeriodicalId":431743,"journal":{"name":"2015 International Conference on Communication Networks (ICCN)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127814614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Neural signal front-end amplifier in 45 nm technology 45纳米技术的神经信号前端放大器
Pub Date : 2015-11-01 DOI: 10.1109/ICCN.2015.43
Jainendra Tripathi, R. S. Tomar, S. Akashe
In this paper, a front-end amplifier is designed in 45nm CMOS technology (previously designed in 180 nm technology) for recording neural signals. This amplifier consists of three stages -(1) a pre-amplifier with a feedback loop, (2) a current gain stage with adjustable gain, and (3) a tunable filter. The first stage is a current-mode pre-amplifier with feedback loop. The feedback loop is used to bypass dc-offset current generated at the electrode-tissue interface. Adjustable current-gain stage is the second stage which is used to adjust the gain of the amplifier by the application of digital signals. Tunable filter (third stage) adjusts the low-pass cut-off frequency for different neural signals. All the stages in the amplifier are current mode circuits. To convert the output current signal of the tunable filter into voltage signal a transimpedance amplifier is used. The measured maximum voltage gain of the amplifier is 72.5 db. The maximum current noise is 23pA/√Hz, and the power consumption is 6μw at 0.8V power supply.
本文采用45nm CMOS技术(之前采用180nm工艺)设计了一个前端放大器,用于记录神经信号。该放大器由三级组成——(1)带反馈回路的前置放大器,(2)增益可调的电流增益级,(3)可调滤波器。第一级是带反馈回路的电流模式前置放大器。反馈回路用于旁路在电极-组织界面产生的直流偏置电流。可调电流增益级是利用数字信号调节放大器增益的第二级。可调滤波器(第三级)调节不同神经信号的低通截止频率。放大器的所有级都是电流型电路。为了将可调谐滤波器的输出电流信号转换成电压信号,使用了一个跨阻放大器。测量到放大器的最大电压增益为72.5 db。最大电流噪声为23pA/√Hz, 0.8V供电时功耗为6μw。
{"title":"Neural signal front-end amplifier in 45 nm technology","authors":"Jainendra Tripathi, R. S. Tomar, S. Akashe","doi":"10.1109/ICCN.2015.43","DOIUrl":"https://doi.org/10.1109/ICCN.2015.43","url":null,"abstract":"In this paper, a front-end amplifier is designed in 45nm CMOS technology (previously designed in 180 nm technology) for recording neural signals. This amplifier consists of three stages -(1) a pre-amplifier with a feedback loop, (2) a current gain stage with adjustable gain, and (3) a tunable filter. The first stage is a current-mode pre-amplifier with feedback loop. The feedback loop is used to bypass dc-offset current generated at the electrode-tissue interface. Adjustable current-gain stage is the second stage which is used to adjust the gain of the amplifier by the application of digital signals. Tunable filter (third stage) adjusts the low-pass cut-off frequency for different neural signals. All the stages in the amplifier are current mode circuits. To convert the output current signal of the tunable filter into voltage signal a transimpedance amplifier is used. The measured maximum voltage gain of the amplifier is 72.5 db. The maximum current noise is 23pA/√Hz, and the power consumption is 6μw at 0.8V power supply.","PeriodicalId":431743,"journal":{"name":"2015 International Conference on Communication Networks (ICCN)","volume":"159 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127356840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Analysis and performance improvement of K-means clustering in big data environment 大数据环境下K-means聚类分析及性能改进
Pub Date : 2015-11-01 DOI: 10.1109/ICCN.2015.9
Purva Rathore, Deepak Shukla
The big data environment is used to support the huge amount of data processing. In this environment tons (i.e. Giga bytes, Tera bytes) of data is processed. Therefore the various online applications where the huge data request are generated are treated using the big data i.e. facebook, google. In this presented work the big data environment is studied and investigated how the data is consumed using the big data and how the supporting tools are working with the Hadoop storage. Furthermore, for keen understanding and investigation, a cluster analysis technique more specifically the K-mean clustering algorithm is implemented through the Hadoop and MapReduce. The clustering is a part of big data analytics where the unlabelled data is processed and utilized to make groups of the data. In addition of that it is observed the traditional k-mean algorithm is not much suitably works with the Hadoop and MapReduce thus small amount of modification is performed on the data processing technique. In addition of that during cluster analysis various issues are found in traditional k-means i.e. fluctuating accuracy, outliers and empty cluster. Therefore a new clustering algorithm with modification on traditional approach of k-means clustering is proposed and implemented. That approach first enhances the data quality by removing the outlier points in datasets and then the bi-part method is used to perform the clustering. The proposed clustering technique implemented using the JAVA, Hadoop and MapReduce finally the performance of the proposed clustering approach is evaluated and compared with the traditional k-means clustering algorithm. The obtained performance shows the effective results and enhanced accuracy of cluster formation with the removal of the de-efficiency. Thus the proposed work is adoptable for the big data environment with improving the performance of clustering.
使用大数据环境来支持海量的数据处理。在这种环境中,要处理大量(即千兆字节、兆字节)的数据。因此,产生大量数据请求的各种在线应用程序都使用大数据进行处理,例如facebook, google。在本文中,作者研究了大数据环境,并调查了数据是如何使用大数据消费的,以及支持工具是如何与Hadoop存储一起工作的。此外,为了深入了解和研究,本文通过Hadoop和MapReduce实现了一种聚类分析技术,更具体地说是k -均值聚类算法。聚类是大数据分析的一部分,其中未标记的数据被处理并用于数据组。此外,观察到传统的k-mean算法不太适合与Hadoop和MapReduce一起工作,因此对数据处理技术进行了少量修改。此外,在聚类分析过程中,传统的k-means还存在各种问题,即波动精度、异常值和空聚类。为此,提出并实现了一种改进传统k均值聚类方法的聚类算法。该方法首先通过去除数据集中的离群点来提高数据质量,然后使用双部分方法进行聚类。利用JAVA、Hadoop和MapReduce实现了本文提出的聚类技术,最后对本文提出的聚类方法的性能进行了评价,并与传统的k-means聚类算法进行了比较。实验结果表明,在去除脱效率后,簇的形成精度得到了提高。因此,本文提出的方法可以应用于大数据环境,提高了聚类的性能。
{"title":"Analysis and performance improvement of K-means clustering in big data environment","authors":"Purva Rathore, Deepak Shukla","doi":"10.1109/ICCN.2015.9","DOIUrl":"https://doi.org/10.1109/ICCN.2015.9","url":null,"abstract":"The big data environment is used to support the huge amount of data processing. In this environment tons (i.e. Giga bytes, Tera bytes) of data is processed. Therefore the various online applications where the huge data request are generated are treated using the big data i.e. facebook, google. In this presented work the big data environment is studied and investigated how the data is consumed using the big data and how the supporting tools are working with the Hadoop storage. Furthermore, for keen understanding and investigation, a cluster analysis technique more specifically the K-mean clustering algorithm is implemented through the Hadoop and MapReduce. The clustering is a part of big data analytics where the unlabelled data is processed and utilized to make groups of the data. In addition of that it is observed the traditional k-mean algorithm is not much suitably works with the Hadoop and MapReduce thus small amount of modification is performed on the data processing technique. In addition of that during cluster analysis various issues are found in traditional k-means i.e. fluctuating accuracy, outliers and empty cluster. Therefore a new clustering algorithm with modification on traditional approach of k-means clustering is proposed and implemented. That approach first enhances the data quality by removing the outlier points in datasets and then the bi-part method is used to perform the clustering. The proposed clustering technique implemented using the JAVA, Hadoop and MapReduce finally the performance of the proposed clustering approach is evaluated and compared with the traditional k-means clustering algorithm. The obtained performance shows the effective results and enhanced accuracy of cluster formation with the removal of the de-efficiency. Thus the proposed work is adoptable for the big data environment with improving the performance of clustering.","PeriodicalId":431743,"journal":{"name":"2015 International Conference on Communication Networks (ICCN)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123452858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Low power application for nano scaled Memristor based 2∶1 multiplexer 基于2∶1多路复用器的纳米忆阻器的低功耗应用
Pub Date : 2015-11-01 DOI: 10.1109/ICCN.2015.7
Arpana Verma, S. Akashe
Now a day market demands compressed devices that operates on low voltage and causes less noise in the output. Advanced nano scale very large integrated circuits are facing significant timing closure challenges especially due to random on chip threshold voltage variations. Memristor can play an important role in improving the scalability and efficiency of existing memory technology. Accordingly this article introduces Memristor based 2:1 multiplexer. Memristor is non linear passive two terminal electrical components relating electric charge. Memristor has dynamic relationship between current and voltage including a memory of past voltage or current. In this paper two main properties of Memristor is highlighted firstly nano scale dimension and another it's non volatile memory characteristics. By using these properties it gives better way to design the circuit as well as it stored output too. With the many advantages of Memristor CMOS it becomes possible to reduce the area on silicon chip. Here many CMOS transistors are replaced by few Memristor and multiplexer is made. All related parameters of multiplexer, are calculated in the cadence virtuoso tool and 45nm technology with 0.7 v operating voltage.
现在,市场每天都需要在低电压下工作、输出噪音更小的压缩设备。先进的纳米级超大集成电路面临着重大的时序关闭挑战,特别是由于随机的片上阈值电压变化。忆阻器在提高现有存储技术的可扩展性和效率方面发挥着重要作用。据此,本文介绍了基于忆阻器的2:1多路复用器。忆阻器是与电荷有关的非线性无源双端电气元件。忆阻器具有电流和电压之间的动态关系,包括对过去电压或电流的记忆。本文重点介绍了忆阻器的两个主要特性:一是纳米尺寸,二是非易失性存储特性。通过利用这些特性,可以更好地设计电路以及存储输出。由于忆阻式CMOS的诸多优点,使其在硅片上的面积减小成为可能。在这里,许多CMOS晶体管被少数忆阻器和多路复用器所取代。多路复用器的所有相关参数均在cadence virtuoso工具和45纳米技术中计算,工作电压为0.7 v。
{"title":"Low power application for nano scaled Memristor based 2∶1 multiplexer","authors":"Arpana Verma, S. Akashe","doi":"10.1109/ICCN.2015.7","DOIUrl":"https://doi.org/10.1109/ICCN.2015.7","url":null,"abstract":"Now a day market demands compressed devices that operates on low voltage and causes less noise in the output. Advanced nano scale very large integrated circuits are facing significant timing closure challenges especially due to random on chip threshold voltage variations. Memristor can play an important role in improving the scalability and efficiency of existing memory technology. Accordingly this article introduces Memristor based 2:1 multiplexer. Memristor is non linear passive two terminal electrical components relating electric charge. Memristor has dynamic relationship between current and voltage including a memory of past voltage or current. In this paper two main properties of Memristor is highlighted firstly nano scale dimension and another it's non volatile memory characteristics. By using these properties it gives better way to design the circuit as well as it stored output too. With the many advantages of Memristor CMOS it becomes possible to reduce the area on silicon chip. Here many CMOS transistors are replaced by few Memristor and multiplexer is made. All related parameters of multiplexer, are calculated in the cadence virtuoso tool and 45nm technology with 0.7 v operating voltage.","PeriodicalId":431743,"journal":{"name":"2015 International Conference on Communication Networks (ICCN)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126196810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
期刊
2015 International Conference on Communication Networks (ICCN)
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