Technology options for 22nm and beyond

Abstract

This paper explores the challenges facing the 22nm process generation and beyond. CMOS transistor architectures such as ultra-thin body, FinFET, and nanowire will be compared and contrasted. Mobility enhancements such as channel stress, alternative orientations, and exotic materials will be explored. Resistance challenges will be reviewed in relation to key process techniques such as silicidation, implantation and anneal. Capacitance challenges with traditional and new architectures will be discussed in light of new materials and processing techniques. The impact of new transistor architectures and enhanced channel materials on traditional junction engineering solutions will be summarized.