Divide-and-conquer in wafer scale array testing

Abstract

Testing of wafer scale arrays is very time consuming if classical loopback testing is used. In this paper, a divide-and-conquer technique for testing wafer scale arrays is presented. The technique is general in the sense that it can be applied to any regular topologies. Although the proposed scheme also suffers from long testing time in the worst case, it is shown to be very efficient for most of the possible fault patterns. Insertion of test points is also considered to physically partition the arrays so that the desired performance can be achieved regardless of the array size.<>