Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63909
D. Landis
Progress in Wafer Scale Integration (WSI) has brought the problems of system level testing into the semiconductor manufacturing arena. Full wafer testing is complicated by the reduced controllability and observability implicit at this level of integration. Under a DARPA sponsored microelectronics research project at the University of South Florida, several monolithic WSI designs are being developed. A Standard Test Interface (STI) is included on each cell or functional module of each design. It will provide support for built-in self-test, scan based test, boundary scan test, and ad hoc module testing schemes. In addition, use of the STI standard can reduce test complexity and cost because all cells on the wafer will be tested using a single probe card. The author's WSI Standard Test Interface is based upon the proposed IEEE P1149.1 test bus standard which has been derived from the JTAG standards. It represents an extended version of the JTAG Test Access Port, and allows for simultaneous initialization, as well as individual programmability, control, and testing of all chip sites in a WSI system.<>
{"title":"A self-test methodology for restructurable WSI","authors":"D. Landis","doi":"10.1109/ICWSI.1990.63909","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63909","url":null,"abstract":"Progress in Wafer Scale Integration (WSI) has brought the problems of system level testing into the semiconductor manufacturing arena. Full wafer testing is complicated by the reduced controllability and observability implicit at this level of integration. Under a DARPA sponsored microelectronics research project at the University of South Florida, several monolithic WSI designs are being developed. A Standard Test Interface (STI) is included on each cell or functional module of each design. It will provide support for built-in self-test, scan based test, boundary scan test, and ad hoc module testing schemes. In addition, use of the STI standard can reduce test complexity and cost because all cells on the wafer will be tested using a single probe card. The author's WSI Standard Test Interface is based upon the proposed IEEE P1149.1 test bus standard which has been derived from the JTAG standards. It represents an extended version of the JTAG Test Access Port, and allows for simultaneous initialization, as well as individual programmability, control, and testing of all chip sites in a WSI system.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114998139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63895
C. Feng, W. Huang, F. Lombardi
Presents an approach for the full diagnosis (detection and location) of baseline interconnection networks implemented in WSI. A multiple fault model as applicable to production of these devices, is assumed. This implies that a totally exhaustive combinatorial fault model is used in the analysis. It is proved that the maximum number of tests for detecting multiple faults (i.e. 2(1+log/sub 2/N), where N is the number of inputs/outputs), can be used to locate and identify multiple faulty switching elements provided that no intermittent and/or transient behaviour is present, i.e. using the definition of no logically undefined and no undetermined outputs are present. The proposed diagnostic technique is based on a process which reveals the switching state of each element on a stage by stage basis using the test set. No additional hardware is therefore required. The proposed technique can be efficiently used in the manufacturing of complex interconnection networks using advanced integration techniques such as WSI.<>
{"title":"Multiple fault detection and location in WSI baseline interconnection networks","authors":"C. Feng, W. Huang, F. Lombardi","doi":"10.1109/ICWSI.1990.63895","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63895","url":null,"abstract":"Presents an approach for the full diagnosis (detection and location) of baseline interconnection networks implemented in WSI. A multiple fault model as applicable to production of these devices, is assumed. This implies that a totally exhaustive combinatorial fault model is used in the analysis. It is proved that the maximum number of tests for detecting multiple faults (i.e. 2(1+log/sub 2/N), where N is the number of inputs/outputs), can be used to locate and identify multiple faulty switching elements provided that no intermittent and/or transient behaviour is present, i.e. using the definition of no logically undefined and no undetermined outputs are present. The proposed diagnostic technique is based on a process which reveals the switching state of each element on a stage by stage basis using the test set. No additional hardware is therefore required. The proposed technique can be efficiently used in the manufacturing of complex interconnection networks using advanced integration techniques such as WSI.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124878965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63900
Yoon-Hwa Choi
The increasing demand for high performance systems has led to the design of systems comprised of a large number of processing elements on a single wafer. This paper presents a distributed diagnosis algorithm for wafer scale systems. Unlike other approaches, the algorithm does not assume diagnostic circuits are fault-free. The algorithm is simple enough to be realized with small circuit overhead. Computer simulation has shown that even for low unit yields, extremely high performance (fault coverage) can be achieved by properly tuning the algorithm parameters.<>
{"title":"Distributed diagnosis for wafer scale systems","authors":"Yoon-Hwa Choi","doi":"10.1109/ICWSI.1990.63900","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63900","url":null,"abstract":"The increasing demand for high performance systems has led to the design of systems comprised of a large number of processing elements on a single wafer. This paper presents a distributed diagnosis algorithm for wafer scale systems. Unlike other approaches, the algorithm does not assume diagnostic circuits are fault-free. The algorithm is simple enough to be realized with small circuit overhead. Computer simulation has shown that even for low unit yields, extremely high performance (fault coverage) can be achieved by properly tuning the algorithm parameters.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116595175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63906
D. Walker
Most wafer-scale processing arrays include bypass switches and wiring to permit signals to be routed around faulty modules. In some cases, the bypass circuitry contains registers to maintain data synchronization. The ideal switch design maximizes routing flexibility and switch yield while minimizing switch area and signal delay. Unfortunately these design goals work at cross-purposes. The goals also vary in importance, depending on the wafer architecture. For example, some architectures can cope with bypass logic failures, while others cannot. The ability to cope with failures may be a function of the failure mode. The author examines a number of bypass switch circuit and layout designs, and how well they meet to the design goals. He uses the DVLASIC distributed catastrophic fault yield simulator to perform yield computations.<>
{"title":"Soft-programmable bypass switch design for defect-tolerant arrays","authors":"D. Walker","doi":"10.1109/ICWSI.1990.63906","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63906","url":null,"abstract":"Most wafer-scale processing arrays include bypass switches and wiring to permit signals to be routed around faulty modules. In some cases, the bypass circuitry contains registers to maintain data synchronization. The ideal switch design maximizes routing flexibility and switch yield while minimizing switch area and signal delay. Unfortunately these design goals work at cross-purposes. The goals also vary in importance, depending on the wafer architecture. For example, some architectures can cope with bypass logic failures, while others cannot. The ability to cope with failures may be a function of the failure mode. The author examines a number of bypass switch circuit and layout designs, and how well they meet to the design goals. He uses the DVLASIC distributed catastrophic fault yield simulator to perform yield computations.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123607659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63910
Y. Choi, T. Jung
Testing of wafer scale arrays is very time consuming if classical loopback testing is used. In this paper, a divide-and-conquer technique for testing wafer scale arrays is presented. The technique is general in the sense that it can be applied to any regular topologies. Although the proposed scheme also suffers from long testing time in the worst case, it is shown to be very efficient for most of the possible fault patterns. Insertion of test points is also considered to physically partition the arrays so that the desired performance can be achieved regardless of the array size.<>
{"title":"Divide-and-conquer in wafer scale array testing","authors":"Y. Choi, T. Jung","doi":"10.1109/ICWSI.1990.63910","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63910","url":null,"abstract":"Testing of wafer scale arrays is very time consuming if classical loopback testing is used. In this paper, a divide-and-conquer technique for testing wafer scale arrays is presented. The technique is general in the sense that it can be applied to any regular topologies. Although the proposed scheme also suffers from long testing time in the worst case, it is shown to be very efficient for most of the possible fault patterns. Insertion of test points is also considered to physically partition the arrays so that the desired performance can be achieved regardless of the array size.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121851739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63877
R. Bourassa, T. Coffman, J. Brewer
Inova has developed a one megabit monolithic static RAM which contains over five million transistors and occupies a die area of approximately 320 square mm. This product has been in production since March, 1988, is fully 883C compliant, is the largest monolithic production memory in the world today, and has demonstrated wafer yields as high as 100%. The product exists in both *8 and *16 organizations, and is fabricated on a 1.2 mu P-well CMOS process. Current delivery rates are tens of thousands of devices per month. This paper reviews Inroute technology, the present state of the existing product, the Inroute yield model, current yield information on the Inova 1 M SRAM and an experimental monolithic eight megabit SRAM being developed jointly by INOVA and Westinghouse to explore the yield and packaging aspects of large area devices for use in military systems. The design combines the INOVA commercial one megabit SRAM, and the Westinghouse volumetrically efficient dual composite packaging approach.<>
{"title":"Progress in WSI SRAM development","authors":"R. Bourassa, T. Coffman, J. Brewer","doi":"10.1109/ICWSI.1990.63877","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63877","url":null,"abstract":"Inova has developed a one megabit monolithic static RAM which contains over five million transistors and occupies a die area of approximately 320 square mm. This product has been in production since March, 1988, is fully 883C compliant, is the largest monolithic production memory in the world today, and has demonstrated wafer yields as high as 100%. The product exists in both *8 and *16 organizations, and is fabricated on a 1.2 mu P-well CMOS process. Current delivery rates are tens of thousands of devices per month. This paper reviews Inroute technology, the present state of the existing product, the Inroute yield model, current yield information on the Inova 1 M SRAM and an experimental monolithic eight megabit SRAM being developed jointly by INOVA and Westinghouse to explore the yield and packaging aspects of large area devices for use in military systems. The design combines the INOVA commercial one megabit SRAM, and the Westinghouse volumetrically efficient dual composite packaging approach.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131136210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63882
L. Whicker, J.J. Zingaro, M. Driver, R. C. Clarke
Describes a new approach to active phased array technology. Here, several modules are fabricated at the same time and placed in a layered structure. The layers include the RF modules, cooling manifold, DC bias distribution, RF manifold, and radiating elements. In this configuration, 16 or more T/R modules are fabricated on a single 3-inch GaAs wafer. The realization of multiple modules on a wafer is made possible by redundancy of circuit elements and novel mechanical switches. Preliminary results on these efforts are presented.<>
{"title":"Re-wafer scale integration: a new approach to active phased arrays","authors":"L. Whicker, J.J. Zingaro, M. Driver, R. C. Clarke","doi":"10.1109/ICWSI.1990.63882","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63882","url":null,"abstract":"Describes a new approach to active phased array technology. Here, several modules are fabricated at the same time and placed in a layered structure. The layers include the RF modules, cooling manifold, DC bias distribution, RF manifold, and radiating elements. In this configuration, 16 or more T/R modules are fabricated on a single 3-inch GaAs wafer. The realization of multiple modules on a wafer is made possible by redundancy of circuit elements and novel mechanical switches. Preliminary results on these efforts are presented.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132851888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63878
R. Berger, A. Bertapelli, R. Frankel, J.J. Hunt, J. Mann, J. Raffel, F. M. Rhodes, A. Soares, C. Woodward
The Programmable Image Processor is a laser-restructurable, wafer-scale device fabricated on a 125-mm wafer using an n-well CMOS process with 2.0 micrometer gates. Yield projections indicate that one wafer has enough devices to construct an array of 16 SIMD-programmable processors and 25 shared memories. The memory array can store two images each 128-by-128 pixels. One run of wafers has been fabricated, and these wafers were undergoing testing and restructuring at the time of publication.<>
{"title":"The Lincoln programmable image-processing wafer","authors":"R. Berger, A. Bertapelli, R. Frankel, J.J. Hunt, J. Mann, J. Raffel, F. M. Rhodes, A. Soares, C. Woodward","doi":"10.1109/ICWSI.1990.63878","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63878","url":null,"abstract":"The Programmable Image Processor is a laser-restructurable, wafer-scale device fabricated on a 125-mm wafer using an n-well CMOS process with 2.0 micrometer gates. Yield projections indicate that one wafer has enough devices to construct an array of 16 SIMD-programmable processors and 25 shared memories. The memory array can store two images each 128-by-128 pixels. One run of wafers has been fabricated, and these wafers were undergoing testing and restructuring at the time of publication.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114619289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63885
T. Kean, J. Gray, B. Pruniaux
In recent years a new class of integrated circuits has emerged which can be configured dynamically to implement gate level logic designs. This class of device is termed configurable hardware. These structures can be used to implement important algorithms with much higher performance than conventional computers and board designs using configurable hardware as a computation engine have been proposed. In many ways wafer scale integration of large configurable hardware systems is very attractive for computational applications and this paper considers a wafer scale version of one particular configurable architecture: Configurable Array Logic (CAL) using CMOS.<>
{"title":"Implementation of configurable hardware using wafer scale integration","authors":"T. Kean, J. Gray, B. Pruniaux","doi":"10.1109/ICWSI.1990.63885","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63885","url":null,"abstract":"In recent years a new class of integrated circuits has emerged which can be configured dynamically to implement gate level logic designs. This class of device is termed configurable hardware. These structures can be used to implement important algorithms with much higher performance than conventional computers and board designs using configurable hardware as a computation engine have been proposed. In many ways wafer scale integration of large configurable hardware systems is very attractive for computational applications and this paper considers a wafer scale version of one particular configurable architecture: Configurable Array Logic (CAL) using CMOS.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129364126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63904
R. Ramaswamy, G. Brebner, D. Aspinall
A methodology for designing large one-dimensional pipelined array processing architectures where a large number of defects can be expected is presented. Central to the methodology is a functional separation at each processing element between the processing core and the inter-cell communication path. Using an 'interconnection harness' which provides the inter-cell communication medium and straps or links the underlying processing cores into a working array, 100% utilisation of the 'healthy' processing elements can be achieved. The harness which snakes across the wafer and forms the backbone of this architecture is made highly reliable and capable of sustaining up to a maximum of N single errors in an N cell array.<>
{"title":"A methodology for wafer scale integration of linear pipelined arrays","authors":"R. Ramaswamy, G. Brebner, D. Aspinall","doi":"10.1109/ICWSI.1990.63904","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63904","url":null,"abstract":"A methodology for designing large one-dimensional pipelined array processing architectures where a large number of defects can be expected is presented. Central to the methodology is a functional separation at each processing element between the processing core and the inter-cell communication path. Using an 'interconnection harness' which provides the inter-cell communication medium and straps or links the underlying processing cores into a working array, 100% utilisation of the 'healthy' processing elements can be achieved. The harness which snakes across the wafer and forms the backbone of this architecture is made highly reliable and capable of sustaining up to a maximum of N single errors in an N cell array.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131378524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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