Optimization of Drain Extended MOS Devices for Reliability in High Switching applications

Abstract

In this work, we investigate the static and transient performance of Drain Extended NMOS (DeNMOS) devices with and without Shallow Trench Isolation (STI). Devices drain-to-source pitch and layout parameters are kept constant, except gate overlap length which is reduced by applying a suitable gate edge termination technique to ensure Safe Operating Area (SOA) and lower the gate charge. A comparative study of optimized STI and NonSTI based DeNMOS for switching applications and gate edge reliability is shown. It is found that the reduction of gate length over the drift region reduces gate to drain coupling charge by more than 60%. We present that a FOM improvement of 55% in STI and 45% in NonSTI DeNMOS w.r.t their respective standard devices can be achieved using gate edge termination techniques without compromising in SOA and gate edge reliability.