Impact of phonon-boundary scattering and multilevel copper-dielectric interconnect system on self-heating of SOI transistors

Abstract

The paper investigates the relevance and impact of nanoscale thermal phenomena (e.g., phonon-boundary scattering) on the thermal performance of state-of-the-art semiconductor device technologies. Moreover, the impact of the multilevel copper-dielectric structure on the total thermal resistance of SOI transistors is demonstrated for the first time. The proposed thermal resistance model incorporates the impact of via separation, metal and dielectric layer thickness, and the dimension of the heated region (e.g., device). The predicted thermal resistance values for a multi-level copper-dielectric interconnect system agree well with the three dimensional finite element simulations. It is concluded that the heat conduction through the Cu-dielectric interconnect network can reduce the thermal resistance of a single SOI transistor by a factor of 3-4, depending on the dimension and specifics of the Cu-dielectric structure and the transistor.