Pub Date : 2007-05-29DOI: 10.1109/TCAPT.2007.898330
R. F. Hill, J.L. Strader
In order to improve the thermal performance of polymeric materials, they can be filled with intrinsically high thermal conductivity fillers that provide heat-conducting paths through the resulting composite. The thermal performance of polymers loaded with platelet-shaped fillers was modeled using finite element analysis in order to provide a prediction of thermal conductivity as a function of variables such as filler thermal conductivity, orientation, and polymer matrix thermal conductivity. Modeling results were compared to experimental data. An unexpectedly strong effect that the matrix conductivity has on the conductivity of the polymer-ceramic composite was predicted by modeling and confirmed experimentally.
{"title":"Rudimentary finite element thermal modeling of platelet-filled polymer-ceramic composites","authors":"R. F. Hill, J.L. Strader","doi":"10.1109/TCAPT.2007.898330","DOIUrl":"https://doi.org/10.1109/TCAPT.2007.898330","url":null,"abstract":"In order to improve the thermal performance of polymeric materials, they can be filled with intrinsically high thermal conductivity fillers that provide heat-conducting paths through the resulting composite. The thermal performance of polymers loaded with platelet-shaped fillers was modeled using finite element analysis in order to provide a prediction of thermal conductivity as a function of variables such as filler thermal conductivity, orientation, and polymer matrix thermal conductivity. Modeling results were compared to experimental data. An unexpectedly strong effect that the matrix conductivity has on the conductivity of the polymer-ceramic composite was predicted by modeling and confirmed experimentally.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133401930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-03-15DOI: 10.1109/STHERM.2005.1412181
K. Etessam-Yazdani, M. Asheghi
The paper focuses on the effect of nano-scale thermal phenomena on the performance of strained-Si transistors. The impact of SiGe underlayer and interface roughness on the lateral thermal conductivity of the transistor channel at room temperature is studied. The experimental data and predictions for thin Si layer thermal conductivity and the solutions of the Boltzmann transport equations (BTE) for phonon transport in the strained-Si/SiGe bilayer configuration are used to estimate the effect of self-heating on some of the key parameters of future generations of strained-Si transistors. The analysis presented shows that, due to the continuous increase of self-heating in the future, the merits of strained-Si transistors will be suppressed, unless various parameters involved in the design of these devices are revised to maintain the existing merits.
{"title":"Sub-continuum thermal analysis of strained-Si/SiGe transistor scaling","authors":"K. Etessam-Yazdani, M. Asheghi","doi":"10.1109/STHERM.2005.1412181","DOIUrl":"https://doi.org/10.1109/STHERM.2005.1412181","url":null,"abstract":"The paper focuses on the effect of nano-scale thermal phenomena on the performance of strained-Si transistors. The impact of SiGe underlayer and interface roughness on the lateral thermal conductivity of the transistor channel at room temperature is studied. The experimental data and predictions for thin Si layer thermal conductivity and the solutions of the Boltzmann transport equations (BTE) for phonon transport in the strained-Si/SiGe bilayer configuration are used to estimate the effect of self-heating on some of the key parameters of future generations of strained-Si transistors. The analysis presented shows that, due to the continuous increase of self-heating in the future, the merits of strained-Si transistors will be suppressed, unless various parameters involved in the design of these devices are revised to maintain the existing merits.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126928335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-03-15DOI: 10.1109/STHERM.2005.1412168
W. Khan, J. Culham, M. Yovanovich
Analytical models are presented for determining heat transfer from in-line and staggered pin-fin heat sinks used in electronic packaging applications. The heat transfer coefficient for the heat sink and the average temperature for the fluid inside the heat sink are obtained from an energy balance over a control volume. In addition, friction coefficient models for both arrangements are developed from published data. The effects of thermal conductivity on the thermal performance are also examined. All models can be applied over a wide range of heat sink parameters and are suitable for use in the design of pin-fin heat sinks. The presented models are in good agreement with existing experimental/numerical data.
{"title":"Modeling of cylindrical pin-fin heat sinks for electronic packaging","authors":"W. Khan, J. Culham, M. Yovanovich","doi":"10.1109/STHERM.2005.1412168","DOIUrl":"https://doi.org/10.1109/STHERM.2005.1412168","url":null,"abstract":"Analytical models are presented for determining heat transfer from in-line and staggered pin-fin heat sinks used in electronic packaging applications. The heat transfer coefficient for the heat sink and the average temperature for the fluid inside the heat sink are obtained from an energy balance over a control volume. In addition, friction coefficient models for both arrangements are developed from published data. The effects of thermal conductivity on the thermal performance are also examined. All models can be applied over a wide range of heat sink parameters and are suitable for use in the design of pin-fin heat sinks. The presented models are in good agreement with existing experimental/numerical data.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122695102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-03-15DOI: 10.1109/STHERM.2005.1412176
U. Vadakkan, Gregory M. Chrysler, Sandeep Sane
A numerical study is performed to characterize the thermal and mechanical performances of silicon/water vapor chambers as heat spreaders for electronics cooling applications and to compare their performance against Cu heat spreaders. 2D flow and energy equations are solved in the vapor and liquid regions, along with conduction in the wall. An equilibrium model for heat transfer and a Brinkman-Forchheimer extended Darcy model for fluid flow are solved in the wick region. In addition to thermal modeling, FEA is also performed to study the impact of the proposed design on die stresses. The study shows that this system can match or thermally perform better than a more standard Cu spreader while also reducing the compressive stress in the Si by as much as 96%. Analysis shows that there are two main factors contributing towards the reduction of stress in the Si die, namely, the better CTE match between the Si die and the Si heat spreader and higher compliance (less stiffness) of the vapor chamber compared to standard heat spreaders. Thus Si vapor chambers provide a good design alternative to a standard Cu heat spreader without compromising on the reliability and performance of the Si.
{"title":"Silicon/water vapor chamber as heat spreaders for microelectronic packages","authors":"U. Vadakkan, Gregory M. Chrysler, Sandeep Sane","doi":"10.1109/STHERM.2005.1412176","DOIUrl":"https://doi.org/10.1109/STHERM.2005.1412176","url":null,"abstract":"A numerical study is performed to characterize the thermal and mechanical performances of silicon/water vapor chambers as heat spreaders for electronics cooling applications and to compare their performance against Cu heat spreaders. 2D flow and energy equations are solved in the vapor and liquid regions, along with conduction in the wall. An equilibrium model for heat transfer and a Brinkman-Forchheimer extended Darcy model for fluid flow are solved in the wick region. In addition to thermal modeling, FEA is also performed to study the impact of the proposed design on die stresses. The study shows that this system can match or thermally perform better than a more standard Cu spreader while also reducing the compressive stress in the Si by as much as 96%. Analysis shows that there are two main factors contributing towards the reduction of stress in the Si die, namely, the better CTE match between the Si die and the Si heat spreader and higher compliance (less stiffness) of the vapor chamber compared to standard heat spreaders. Thus Si vapor chambers provide a good design alternative to a standard Cu heat spreader without compromising on the reliability and performance of the Si.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117006593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-03-15DOI: 10.1109/STHERM.2005.1412166
Guoping Xu, L. Follmer
A methodology to develop a thermal solution was demonstrated through a case study of upgrading processors in an existing cabinet, thereby increasing the power envelope of the processors. The Sun Fire E25K server, based on UltraSparc IV (USIV), was used as an example in this paper. This high-end server utilized the same physical configuration as in the preceding generation Sun Fire 15K server accommodating seventy-two UltraSparc III (USIII) processors. Extensive experimental investigations have been carried out to characterize the thermal performance in the Sun Fire 15K including cabinet-level, board-level, CPU air-cooled heat sink, and fan/fan tray thermal characterization. Solutions were proposed by combining the experimental data with flow network modeling, validated analytical methods and numerical modeling. Solutions included a new CPU heat sink design and air flow optimization at the board and cabinet level. The proposed solutions were verified in the existing product and successfully implemented in the new product.
通过升级现有机柜中的处理器，从而增加处理器的功率包络度的案例研究，展示了开发热解决方案的方法。本文以基于UltraSparc IV (USIV)的Sun Fire E25K服务器为例。这台高端服务器使用了与上一代Sun Fire 15K服务器相同的物理配置，可容纳72个UltraSparc III (USIII)处理器。为了表征Sun Fire 15K的热性能，进行了大量的实验研究，包括机柜级、板级、CPU风冷散热器和风扇/风扇托盘的热特性。将实验数据与流网络模型、验证的解析方法和数值模拟相结合，提出了解决方案。解决方案包括一个新的CPU散热器设计和优化气流在板和机柜级。提出的解决方案在现有产品中得到验证，并在新产品中成功实现。
{"title":"Thermal solution development for high-end server systems","authors":"Guoping Xu, L. Follmer","doi":"10.1109/STHERM.2005.1412166","DOIUrl":"https://doi.org/10.1109/STHERM.2005.1412166","url":null,"abstract":"A methodology to develop a thermal solution was demonstrated through a case study of upgrading processors in an existing cabinet, thereby increasing the power envelope of the processors. The Sun Fire E25K server, based on UltraSparc IV (USIV), was used as an example in this paper. This high-end server utilized the same physical configuration as in the preceding generation Sun Fire 15K server accommodating seventy-two UltraSparc III (USIII) processors. Extensive experimental investigations have been carried out to characterize the thermal performance in the Sun Fire 15K including cabinet-level, board-level, CPU air-cooled heat sink, and fan/fan tray thermal characterization. Solutions were proposed by combining the experimental data with flow network modeling, validated analytical methods and numerical modeling. Solutions included a new CPU heat sink design and air flow optimization at the board and cabinet level. The proposed solutions were verified in the existing product and successfully implemented in the new product.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128750856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-03-15DOI: 10.1109/STHERM.2005.1412170
C. Lasance, H. Eggink
One way of cooling electronic devices is through enlarging the surface that is in contact with a fluid (usually air) by attaching a heat sink. Since literally thousands of heat sinks are available many designers are confronted with the question: which one? Very often the designer's choice is based on cost and manufacturer's data. Unfortunately, this data cannot be used with confidence because they are almost exclusively based on measurements in a closed duct, thereby disregarding bypass effects and inflow conditions. CFD modeling is no option unless time, a supercomputer and a calibration laboratory are available. This paper discusses a method to rank heat sinks given a certain application. The measurement is based on the extraction of the average heat transfer coefficient from time-dependent temperature curves as a function of velocity and bypass. Scaling the measured effective heat transfer coefficient by mass, volume, weight or height provides several performance metrics allowing designers a novel way of ranking heat sinks in conditions that resemble the application.
{"title":"A method to rank heat sinks in practice: the heat sink performance tester","authors":"C. Lasance, H. Eggink","doi":"10.1109/STHERM.2005.1412170","DOIUrl":"https://doi.org/10.1109/STHERM.2005.1412170","url":null,"abstract":"One way of cooling electronic devices is through enlarging the surface that is in contact with a fluid (usually air) by attaching a heat sink. Since literally thousands of heat sinks are available many designers are confronted with the question: which one? Very often the designer's choice is based on cost and manufacturer's data. Unfortunately, this data cannot be used with confidence because they are almost exclusively based on measurements in a closed duct, thereby disregarding bypass effects and inflow conditions. CFD modeling is no option unless time, a supercomputer and a calibration laboratory are available. This paper discusses a method to rank heat sinks given a certain application. The measurement is based on the extraction of the average heat transfer coefficient from time-dependent temperature curves as a function of velocity and bypass. Scaling the measured effective heat transfer coefficient by mass, volume, weight or height provides several performance metrics allowing designers a novel way of ranking heat sinks in conditions that resemble the application.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"249 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130749750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-03-15DOI: 10.1109/STHERM.2005.1412184
Puyan Dadvar, K. Skadron
Hardware and software techniques for controlling a microprocessor's power and cooling have the undesirable side effect of creating a security risk. They allow a malicious program to control the chip's operating temperature and potentially cause denial of service or even permanent damage. The paper provides an overview of the various vulnerabilities, their costs, and offers preliminary suggestions on how to reduce these risks.
{"title":"Potential thermal security risks","authors":"Puyan Dadvar, K. Skadron","doi":"10.1109/STHERM.2005.1412184","DOIUrl":"https://doi.org/10.1109/STHERM.2005.1412184","url":null,"abstract":"Hardware and software techniques for controlling a microprocessor's power and cooling have the undesirable side effect of creating a security risk. They allow a malicious program to control the chip's operating temperature and potentially cause denial of service or even permanent damage. The paper provides an overview of the various vulnerabilities, their costs, and offers preliminary suggestions on how to reduce these risks.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115536468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-03-15DOI: 10.1109/STHERM.2005.1412197
M. Rencz
After an introductory discussion of the thermal issues in stacked die packages in general, two major subjects are discussed in the paper: the qualification of die attach in stacked die structures and the questions of compact thermal modeling. An overview is given about the currently used techniques for the qualification of the die attach for failure analysis in stacked structures. The third part of the paper presents the state-of-the-art and the major issues of compact thermal modeling of stacked die packages.
{"title":"Thermal issues in stacked die packages","authors":"M. Rencz","doi":"10.1109/STHERM.2005.1412197","DOIUrl":"https://doi.org/10.1109/STHERM.2005.1412197","url":null,"abstract":"After an introductory discussion of the thermal issues in stacked die packages in general, two major subjects are discussed in the paper: the qualification of die attach in stacked die structures and the questions of compact thermal modeling. An overview is given about the currently used techniques for the qualification of the die attach for failure analysis in stacked structures. The third part of the paper presents the state-of-the-art and the major issues of compact thermal modeling of stacked die packages.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122176192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-03-15DOI: 10.1109/STHERM.2005.1412203
H. Oprins, C. Nicole, J. Baret, G. Van der Veken, C. Lasance, M. Baelmans
In this paper, the capability of a novel cooling system for microchannels based on the principle of electrowetting is examined. To start with, the electrowetting effect in microchannels is experimentally investigated. Next, based upon these results, the cooling capacity of the proposed system is theoretically investigated. It can be concluded that the proposed system is promising, especially when frequencies in the range of a few Hz can be achieved.
{"title":"On-chip liquid cooling with integrated pump technology","authors":"H. Oprins, C. Nicole, J. Baret, G. Van der Veken, C. Lasance, M. Baelmans","doi":"10.1109/STHERM.2005.1412203","DOIUrl":"https://doi.org/10.1109/STHERM.2005.1412203","url":null,"abstract":"In this paper, the capability of a novel cooling system for microchannels based on the principle of electrowetting is examined. To start with, the electrowetting effect in microchannels is experimentally investigated. Next, based upon these results, the cooling capacity of the proposed system is theoretically investigated. It can be concluded that the proposed system is promising, especially when frequencies in the range of a few Hz can be achieved.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128781684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-03-15DOI: 10.1109/STHERM.2005.1412186
W. Liu, M. Asheghi
The paper investigates the relevance and impact of nanoscale thermal phenomena (e.g., phonon-boundary scattering) on the thermal performance of state-of-the-art semiconductor device technologies. Moreover, the impact of the multilevel copper-dielectric structure on the total thermal resistance of SOI transistors is demonstrated for the first time. The proposed thermal resistance model incorporates the impact of via separation, metal and dielectric layer thickness, and the dimension of the heated region (e.g., device). The predicted thermal resistance values for a multi-level copper-dielectric interconnect system agree well with the three dimensional finite element simulations. It is concluded that the heat conduction through the Cu-dielectric interconnect network can reduce the thermal resistance of a single SOI transistor by a factor of 3-4, depending on the dimension and specifics of the Cu-dielectric structure and the transistor.
{"title":"Impact of phonon-boundary scattering and multilevel copper-dielectric interconnect system on self-heating of SOI transistors","authors":"W. Liu, M. Asheghi","doi":"10.1109/STHERM.2005.1412186","DOIUrl":"https://doi.org/10.1109/STHERM.2005.1412186","url":null,"abstract":"The paper investigates the relevance and impact of nanoscale thermal phenomena (e.g., phonon-boundary scattering) on the thermal performance of state-of-the-art semiconductor device technologies. Moreover, the impact of the multilevel copper-dielectric structure on the total thermal resistance of SOI transistors is demonstrated for the first time. The proposed thermal resistance model incorporates the impact of via separation, metal and dielectric layer thickness, and the dimension of the heated region (e.g., device). The predicted thermal resistance values for a multi-level copper-dielectric interconnect system agree well with the three dimensional finite element simulations. It is concluded that the heat conduction through the Cu-dielectric interconnect network can reduce the thermal resistance of a single SOI transistor by a factor of 3-4, depending on the dimension and specifics of the Cu-dielectric structure and the transistor.","PeriodicalId":256936,"journal":{"name":"Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005.","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121882356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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